JPH0946230A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To constitute a D/A converter to be compact without the increase of elements owing to multiple bits. SOLUTION: Voltage sources V1 and V2 are prepared in accordance with '0' and '1' of digital input. A capacitor C1 is connected to the sources through transfer gates TG1 and TG2. A capacitor C2 is connected to the capacitor C1 through a transfer gate TG3. A charge-voltage conversion circuit 1 is connected to the terminal of the capacitor C2 through a transfer gate TG4 and a sample-and-hold circuit 2 is connected to the output. A clock generation circuit 3 generating control clocks driving the transfer gates TG1-TG4 in synchronizing with respective bit data of digital data which are supplied from LSB in order is provided. The charging of C1 by V1 and V2 responding to bit data from LSB and charge distribution between C1 and C2 are repeated and the charge quantity of C2 is voltage-converted so as to obtain analog output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A converter which combines a transfer gate and a capacitor to convert digital data into analog data by utilizing charge charging / discharging.

[0002]

2. Description of the Related Art A D / A converter is usually composed of a combination of a resistor and a switch. Typically, an R-2R circuit that obtains a voltage according to bit data from a reference voltage and combines it with a switch is used,
There is a resistance ladder type in which a switch is combined with a ladder resistor that divides the reference voltage.

[0003]

In the method (1), the number of elements increases in proportion to the number of bits, and in the method (2), the number of elements increases in proportion to the square of the number of bits. Therefore, the multi-bit D / A converter has a problem that the D / A conversion unit becomes large.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a D / A converter which does not increase the number of elements due to the increase in the number of bits and can be constructed compactly. .

[0005]

A D / A converter according to the present invention includes first and second voltage sources prepared corresponding to digital data "0" and "1", respectively. , A first capacitor connected to the second voltage source via the first and second transfer gates respectively and charged by the selected voltage source, and a first capacitor connected to the first capacitor via the third transfer gate. And a charge-voltage conversion circuit connected to a terminal of the second capacitor via a fourth transfer gate, and an LSB. A clock generation circuit that generates a clock for driving the first to fourth transfer gates in synchronization with each bit data of the digital data sequentially supplied from 1 con The charge of the second capacitor is performed after the charge of the second capacitor is charged, and the charge is distributed between the first capacitor and the second capacitor between the charging of each bit data and MSB is repeated. Is characterized in that the voltage is converted to obtain an analog output.

The D / A converter according to the present invention also includes
Via first and second voltage sources prepared corresponding to digital data "0" and "1" respectively, and via the first and second transfer gates to the first and second voltage sources, respectively. A second capacitor connected and charged by a selected voltage source, and a second capacitor connected to the first capacitor through a third transfer gate to perform charge distribution between the first capacitor. Capacitor, a charge-voltage conversion circuit connected to the terminal of the second capacitor via the fourth transfer gate, a sample hold circuit connected to the output of the charge-voltage conversion circuit, and LSB in order. In synchronization with each bit data of the supplied digital data, the first to
A clock generating circuit for generating a clock for driving a fourth transfer gate, the first capacitor is charged in order from the LSB in accordance with bit data, and the first capacitor is charged between charging of each bit data. The charge is distributed between the capacitor and the second capacitor, the same operation is repeated up to the MSB, and then the charge of the second capacitor is converted into a voltage to obtain an analog output.

According to the present invention, the combination of the transfer gate and the capacitor is used to charge the first capacitor by the voltage source corresponding to the bit data of each bit data of the input digital data, An analog output can be obtained by repeating the operation of charge distribution between the second capacitors. In this system, the number of elements used does not increase even if the number of bits increases, and since no resistor is used, it can be made extremely compact especially when integrated into an IC.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a D / A converter according to an embodiment of the present invention. A first voltage source V1 and a second voltage source V2 are prepared corresponding to the binary values "0" and "1" of the input digital data, respectively. These first and second voltage sources V1 and V2 are predetermined constant voltage sources that satisfy V1> V2.

A first capacitor C1 is connected to the first and second voltage sources V1 and V2 via first and second transfer gates TG1 and TG2. These transfer gates T
G1 and TG2 are controlled in synchronization with each bit data of digital data sequentially supplied from the LSB as described later, and when the bit data is "0", the first transfer gate T
When G1 is driven on and the bit data is "1", the second
The transfer gate TG2 is driven to be turned on. That is, the first capacitor C1 is charged by the first voltage source V1 when the bit data is “0”, and is charged by the second voltage source V1 when the bit data is “1”.
Charged by 2.

At the reference terminal of the first capacitor C1, VCOM set at the middle of the first and second voltage sources V1 and V2.
Is applied. The second capacitor C2 sharing the reference terminal is connected to the terminal of the first capacitor C1 via the third transfer gate TG3. The second capacitor C2 is the first capacitor C1 when the third transfer gate TG3 is driven on.
The charge is distributed between the first capacitor C1 and the first capacitor C1 in this embodiment. The first capacitor C1 is sequentially charged by the bit data, and the third transfer gate TG3 is ON-driven during the charging operation so that the first and second capacitors C1,
The charge is distributed between C2.

The charge-voltage conversion circuit 1 is connected to the terminal of the second capacitor C2 via the fourth transfer gate TG4. The charge-voltage conversion circuit 1 includes an operational amplifier O.
It is composed of P1 and a feedback capacitor C3 and also serves as an impedance conversion circuit. Fourth transfer gate TG
4 is turned on after the D / A conversion operation by charging and charge distribution in the first and second capacitors C1 and C2 is completed, whereby the analog output voltage is obtained in the charge-voltage conversion circuit 1. Become. The feedback capacitor C3 has a transfer gate TG6 for short-circuiting it for circuit initialization.
Is provided.

The output of the charge-voltage conversion circuit 1 is connected to a sample hold circuit 2 composed of a transfer gate TG7, a capacitor C4, and an operational amplifier OP2. In addition, D / A is placed between both ends of the second capacitor C2.
A transfer gate TG5 is provided for initialization in which the second capacitor C2 is short-circuited to discharge all the electric charges in the initial stage of the conversion operation.

In the case of this embodiment, the transfer gates TG1 to T
A bidirectional CMOS transfer gate is used for G7. The control clocks S1 to S7 supplied to the transfer gates TG1 to TG7 are generated by the clock generation circuit 3 in synchronization with the digital data sequentially supplied from the LSB. Control clock S by this clock generation circuit 3
The timing and logic of occurrence of 1 to S7 are as follows.
For each data bit, the control clock S1 or S2 is generated according to the "0" or "1". The control clock S3 is generated during the charging operation by each bit data. The above is the basic operation of D / A conversion.

After repeating the above operation, a control clock S4 is generated to operate the charge-voltage conversion circuit 1. A control clock S6 for initializing the charge-voltage conversion circuit 1 is generated at an appropriate timing during that period. After the analog output is obtained in the charge-voltage conversion circuit 1, the control clocks S7 and S5 are generated to sample and hold the analog output and initialize the second capacitor C2.

The D / A conversion operation in this embodiment will be described with reference to FIG. 2 by taking the case of 2-bit data as an example. 2 shows LSB of 2-bit data and "0" of the second bit,
Combination of "1" and first capacitor C1 in each case
2 shows the state of voltage change due to the charge voltage and the charge distribution between the first and second capacitors C1 and C2. As described above, when the LSB is "0", the electric charge of C1 (V1-VCOM) is charged in the first capacitor C1 and "1" is charged.
Then, the electric charge of C1 (V2-VCOM) is charged.
Next, the third transfer gate TG3 short-circuits the first and second capacitors C1 and C2, and the charge is distributed. In the case of this embodiment, C1 = C2, so the LSB is
If is "0", Va = (V1 + VCOM) / 2, "1"
In this case, a voltage Vb = (V2 + VCOM) / 2 is obtained.

Next, when the third transfer gate TG3 is turned off and the second bit data is input, the "0" and "1" thereof are generated.
Similarly, the first capacitor is charged, and then the third transfer gate TG3 is turned on, and the charge is distributed. As a result, in the order of “0”, “0” from LSB, Vc1 = (V1 + Va) / 2, and in the case of “1”, “0”, Vc2 = (V1 + Vb) / 2, “0”, “1”. In this case, when Vc3 = (Va + V2) / 2, "1", "1", a voltage Vc4 = (Vb + V2) / 2 is obtained in the second capacitor C2. That is, a voltage Vc1>Vc2>Vc3> Vc4 corresponding to the size of the digital data is obtained. Even in the case of digital data of 3 bits or more, the magnitude relationship of the voltages obtained after the final charge redistribution described above does not change, and the D / A conversion is similarly performed.

In FIG. 3, specifically, the input data is 3-bit data, and the LSB = "0", the second bit = "0",
The circuit operation of FIG. 1 when MSB = “1” is shown together with the control clock. When the LSB data "0" is input, the clock generation circuit 3 detects the "0" and outputs the control clock S1 = "H". As a result, the first voltage source V1 charges the first capacitor C1 (t1).
At this time, at the same time, the control clocks S5 and S7 become “H”, the second capacitor C2 is initialized, and the sample hold circuit 2 performs sample hold of the previous data.

Next, at time t2, the control clock S3 is "H".
And the third transfer gate TG3 is turned on,
The charge is divided into two between the first capacitor C1 and the second capacitor C2. At this time, at the same time, the control clock S6 becomes "H", and the capacitor C3 of the charge-voltage conversion circuit 1
Is initialized.

Next, for the data "0" of the second bit, the control clock S1 becomes "H" in the same manner, charging is performed by the first voltage source V1 (t3), and then the control clock S3 becomes "H". H ″, and charge is distributed (t
4). When the MSB data “1” is input, the control clock S2
Becomes "H" and charging is performed by the second voltage source V2 (t5), and subsequently the control clock S3 becomes "H" and charge is distributed (t6).

Simultaneously with the charge distribution of the MSB data, the control clock S4 becomes "H", the fourth transfer gate TG4 is turned on, and the charge-voltage conversion circuit 1
And the first and second capacitors C1 and C2 are connected in parallel, and outputs an analog output voltage obtained by converting the charge amount into a voltage value. The obtained analog voltage is transferred to and held in the capacitor C4 of the sample hold circuit 2 when the control clock S7 becomes "H" next, and is output by the voltage follower. Simultaneously with this sample hold operation, the second capacitor C2 is discharged and the next digital data conversion operation is started.

A clock generation circuit 3 for controlling the above operations
FIG. 4 and FIG. 5 show the specific configuration of the above and its operation timing. In brief, this circuit is based on the basic clock C.
LK and data clock DCLK for eight clock cycles thereof
Based on the above, various timing signals are generated by the timing circuit 41 mainly composed of the D-type flip-flop,
Depending on the combinational logic of the obtained timing signals, control clocks S3 to S having a predetermined timing and width regardless of whether the data is "1" or "0" in the cycle of the data clock DCLK.
7 is generated.

On the other hand, a shift register 42 for performing parallel / serial conversion of bit data and a reference clock CLK
There is provided a 1/2 divider circuit 43 composed of a D-type flip-flop that generates the shift clock SCK based on Data bits Bit1 to Bit3 are parallel (in the case of serial data, converted to parallel data), DCLK
Shift clock S from the 1/2 frequency divider circuit 43, which is taken into the shift register 42 by the load control signal generated at the change point of and is initialized by the same load control signal.
The serial data is sequentially converted from LSB by CK and output. Then, according to the logic of the output data and the reference clock CLK, "1" and "0" of bit data are obtained.
Control clock S1, whose "H" and "L" change according to
Generate S2.

As described above, according to this embodiment, D / A conversion can be performed by combining the transfer gate and the capacitor. When the number of bits of the input digital data increases, the conversion operation cycle T of FIG. 3 changes, but the circuit configuration of FIG. 1 does not change and the number of elements does not increase. Moreover, since the elements used are the transfer gate, the capacitor, and the operational amplifier, and no resistor is used, the circuit can be made into a compact IC.

In the embodiment, the reference potential VCOM applied to the reference terminal may be a zero potential, but when the circuit is integrated into an IC, it is preferable that the intermediate potential of the power supply is the operating point of the operational amplifier OP1. First and second voltage sources V1 and V2
An arbitrary value can be selected within the range of the power source, but it is advantageous that the difference from the reference potential VCOM is large because the charged charge amount can be increased. The bit number n of the input digital data, the amount of electric charge is required to be sufficiently larger than 2 ^n, D / A converter can be the number of bits is limited from this point.

[0025]

As described above, according to the present invention, the charge and distribution of charges by the combination of the transfer gate and the capacitor are utilized to prevent an increase in the number of elements due to the number of bits.
A D / A converter that can be made compact can be obtained.

[Brief description of drawings]

FIG. 1 shows a D / A converter according to an embodiment of the present invention.

FIG. 2 shows a basic operation of D / A conversion of the embodiment.

FIG. 3 shows a specific D / A conversion operation of the same embodiment.

FIG. 4 shows a specific configuration example of a clock generation circuit according to the same embodiment.

FIG. 5 shows operation waveforms of the clock generation circuit.

[Explanation of symbols]

V1 ... 1st voltage source, V2 ... 2nd voltage source, C1 ... 1st
, C2 ... Second capacitor, 1 ... Charge-voltage conversion circuit, 2 ... Sample hold circuit, 3 ... Clock generation circuit, TG1 ... First transfer gate, TG2 ... Second transfer gate, TG3 ... Third Transfer gate, TG4 ... 4th
Transfer gate.

Claims (2)

[Claims] 1. A first voltage source and a second voltage source prepared corresponding to digital data "0" and "1" respectively, and a first voltage source and a second voltage source respectively for the first voltage source and the second voltage source. Charges are transferred between a first capacitor connected through the transfer gate and charged by a selected voltage source, and a first capacitor connected to the first capacitor through the third transfer gate. Second to distribute
Capacitor, a charge-voltage conversion circuit connected to the terminal of this second capacitor through a fourth transfer gate, and the first data in synchronization with each bit data of the digital data sequentially supplied from LSB. A clock generating circuit for generating a clock for driving a fourth transfer gate, the first capacitor is charged in order from the LSB according to bit data, and the first capacitor is charged between charging of each bit data. The charge is distributed between the second capacitor and the second capacitor, the same operation is repeated up to the MSB, and then the charge of the second capacitor is converted into a voltage to obtain an analog output. D / A converter. 2. A first and a second voltage source prepared corresponding to digital data "0" and "1" respectively, and a first and a second voltage source respectively for the first and second voltage sources. Charges are transferred between a first capacitor connected through the transfer gate and charged by a selected voltage source, and a first capacitor connected to the first capacitor through the third transfer gate. Second to distribute
Capacitor, a charge-voltage conversion circuit connected to the terminal of the second capacitor via the fourth transfer gate, a sample hold circuit connected to the output of the charge-voltage conversion circuit, and LSB in order. A clock generation circuit that generates a clock for driving the first to fourth transfer gates in synchronization with each bit data of the supplied digital data, and the first data is output in order from the LSB in accordance with the bit data. The capacitor is charged, the charge is distributed between the first capacitor and the second capacitor between the charging of each bit data, the same operation is repeated up to MSB, and then the charge of the second capacitor A D / A converter characterized in that the voltage is converted into an analog output.