WO2020233818A1

WO2020233818A1 - Voltage to time converter, analog to digital converter, and method for converting an analog voltage

Info

Publication number: WO2020233818A1
Application number: PCT/EP2019/063350
Authority: WO
Inventors: Siddiqui WAQAS; Okko JARVINEN; Vishnu UNNIKRISHNAN; Marko Kosunen; Kari Stadius; Jussi Ryynanen
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2019-05-23
Filing date: 2019-05-23
Publication date: 2020-11-26
Also published as: CN113853748A

Abstract

Voltage to time converter comprises a differential input (201) with a first node (301) and a second node (302), for receiving an input voltage in the form of a potential difference between said first and second nodes (301, 302). A clock input (202) is provided for receiving a clock signal (CK), and a sample and hold circuit (203) is coupled to said differential input (201) for temporarily storing a sample of said input voltage according to a sampling schedule defined by said clock signal (CK). A level shifter (204) is coupled to said sample and hold circuit (203) for controllably shifting a level of the stored sample to produce a level-shifted sample. A ramp generator (205) generates a ramp voltage according to a conversion schedule defined by said clock signal (CK). A comparator (206) is configured to compare the generated ramp voltage to a threshold and to output a stop signal (STOP) in response to said ramp voltage reaching said threshold. Said ramp generator (205) is configured to use said level-shifted sample as an offset in generating said ramp voltage.

Description

VOLTAGE TO TIME CONVERTER, ANALOG TO DIGITAL CONVERTER, AND METHOD FOR CONVERTING AN ANALOG VOLTAGE FIELD OF THE INVENTION

The invention relates to the technical field of analog to digital conversion. In particular the in vention relates to the conversion of an analog voltage to time domain as a part of a time-domain / time-based ADC.

BACKGROUND OF THE INVENTION

High-performance analog to digital converters (ADCs) are needed in various applications of microelec- tronics, including but not being limited to wireless communications. Time-domain / time-based ADC, also known by the acronym TBADC, is a particular kind of analog to digital conversion in which each sample of an incoming analog voltage signal is first converted to time domain and then further into a digital value.

Factors to be considered in the design of high- performance ADC circuits comprise resolution, through put, dynamic range, linearity, power consumption, and chip area. These factors may place mutually contradict- ing requirements: for example it would often be possible to enhance resolution or throughput by using more power and/or chip area, but on the other hand this may not be desirable or even not possible.

There exists a need for ADC solutions that can effectively combine structural simplicity, reasonable dynamic range, high sampling rate, good linearity, low power consumption, and small chip area. SUMMARY

It is an object of the invention to provide a voltage to time converter, an analog to digital con verter, and a method for use in analog to digital con- version that combine structural simplicity, reasonable dynamic range, high sampling rate, good linearity, low power consumption, and small chip area.

The foregoing and other objects are achieved by the features of the independent claims. Further im- plementation forms are apparent from the depending claims, the description, and the drawings.

According to a first aspect there is provided a voltage to time converter, hereinafter VTC. The VTC comprises a differential input with a first node and a second node, for receiving an input voltage in the form of a potential difference between said first and second nodes. The VTC comprises a clock input for receiving a clock signal, and a sample and hold circuit coupled to said differential input for temporarily storing a sample of said input voltage according to a sampling schedule defined by said clock signal. The VTC comprises a level shifter coupled to said sample and hold circuit for controllably shifting a level of the stored sample to produce a level-shifted sample, a ramp generator for generating a ramp voltage according to a conversion schedule defined by said clock signal, and a comparator configured to compare the generated ramp voltage to a threshold and to output a stop signal in response to said ramp voltage reaching said threshold. Said ramp generator is configured to use said level-shifted sample as an offset in generating said ramp voltage.

According to an embodiment the VTC is config ured to make a timing of said stop signal with reference to said clock signal dependent on a value of said level- shifted sample. This involves the advantage that a con cise set of start and stop signals can be conducted to a subsequent time to digital converter for producing a digital output value.

According to an embodiment said level shifter is a reference-free level shifter that comprises a plu rality of capacitances and a corresponding plurality of switches for controllably connecting said plurality of capacitances to respective constant potential rails of said VTC according to a level-shifting schedule defined by said clock signal. This involves the advantage that level shifting of the desired magnitude can be made without the cost in power consumption, silicon area, and/or external connections that the use of a dedicated reference source would mean.

According to an embodiment said level-shifting schedule conforms with said sampling schedule so that said plurality of switches are configured to controlla bly connect respective ones of said plurality of capac itances to said constant potential rails in synchronism with said temporary storing of samples of input voltage in said sample and hold circuit. This involves the ad vantage that the operation of the VTC can be appropri ately timed, and only a very small number of synchro nizing signals are needed.

According to an embodiment said plurality of capacitances comprise a first capacitance and a second capacitance. Said plurality of switches are configured to controllably charge said first capacitance to an op erating voltage of the VTC and said second capacitance to a zero voltage according to said level-shifting schedule. Said plurality of switches are configured to controllably connect said first and second capacitances to said sample and hold circuit according to said level- shifting schedule, for producing said level-shifted sam ple as a combination of said stored sample and the volt ages to which said first and second capacitances were charged. This involves the advantage that the reference- free level shifter can be implemented in a simple and robust manner that is easily scalable to various needs and circuit configurations.

According to an embodiment said sample and hold circuit comprises bootstrapped switches that implement said coupling to said differential input. This involves the advantage that the linearity of the input is good, with only very little - if any - dependence between input levels and input impedance.

According to an embodiment said ramp generator comprises a current source, and an impedance buffer at an output of said current source for boosting an output impedance of said current source. This involves the ad vantage of enabling good linearity of the ramp generator while simultaneously allowing for a wide range of pos sible offset values.

According to an embodiment said ramp generator comprises one or more conversion switches for control- lably forming a capacitive feedback coupling across said impedance buffer through said sample and hold circuit and said level shifter according to said conversion schedule. This involves the advantage that the stored sample can be made to affect the voltage level of the generated ramp in a robust and scalable manner.

According to an embodiment said impedance buffer is an inverter. This involves the advantage of low power consumption, and avoidance of the use of fast, high-precision operational amplifiers with wide input frequency range.

According to an embodiment said comparator com prises a chain of one or more inverters so that said threshold is an inversion threshold voltage of said chain of one or more inverters. This involves the ad vantage of allowing the avoidance of more complicated comparator circuits, as well as allowing to use the inherent inversion threshold voltage of the inverters in the comparison. According to a second aspect there is provided an analog to digital converter that comprises a VTC of the kind described above and a time to digital converter coupled to said VTC to receive a stop signal from said VTC and configured to convert into digital form a de tected length of time between said stop signal and a preceding start signal.

According to an embodiment said VTC is config ured to deliver said clock signal in at least one of a direct or inverted form as said start signal to said time to digital converter. This involves the advantage of enabling the delivery of a start signal in good syn chronism with the operation of the VTC.

According to a third aspect there is provided a method for performing voltage to time conversion. The method comprises temporarily storing a sample of a dif ferential input voltage according to a sampling schedule defined by a clock signal, shifting a level of the stored sample to produce a level-shifted sample, and generating a ramp voltage according to a conversion schedule de fined by said clock signal. The method comprises using said level-shifted sample as an offset in generating said ramp voltage, comparing the generated ramp voltage to a threshold, and outputting a stop signal in response to said ramp voltage reaching said threshold.

According to an embodiment said offset in said ramp voltage makes timing of said stop signal with ref erence to said clock signal dependent on a value of said level-shifted sample. This involves the advantage that a concise set of start and stop signals can be conducted to a subsequent time to digital converter for producing a digital output value.

According to an embodiment said shifting of the level of the stored sample comprises alternately con necting each of a plurality of capacitances to respec tive constant potential rails and together into combi nation with the stored sample, according to a level- shifting schedule defined by the clock signal. This in volves the advantage that level shifting of the desired magnitude can be made without the cost in power con sumption, silicon area, and/or external connections that the use of a dedicated reference source would mean.

According to an embodiment said connecting of each of said plurality of capacitances to respective constant potential rails comprises connecting one of said plurality of capacitances to an operating voltage of the voltage to time converter performing said voltage to time conversion, and connecting another of said plu rality of capacitances (303, 304) to a zero voltage. This involves the advantage that the reference-free level shifter can be implemented in a simple and robust manner that is easily scalable to various needs and circuit configurations.

According to an embodiment said comparing of the generated ramp voltage to said threshold comprises inputting the generated ramp voltage to a chain of one or more inverters so that said threshold is an inversion threshold voltage of said chain of one or more invert ers. This involves the advantage of allowing the avoid ance of more complicated comparator circuits, as well as allowing to use the inherent inversion threshold voltage of the inverters in the comparison.

According to a fourth aspect there is provided a method for performing analog to digital conversion, comprising using a method of the kind described above to perform analog to time conversion, and using a method of time to digital conversion to convert into digital form a detected length of time between said stop signal and a preceding start signal.

According to an embodiment the method comprises using at least one of a rising edge and a falling edge of said clock signal as said start signal. This involves the advantage of enabling the delivery of a start signal in good synchronism with the operation of the VTC. BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and constitute a part of this specification, illustrate ad vantageous embodiments and together with the description help to explain the principles introduced above. In the drawings :

Figure 1 illustrates the two stages of a TBADC, figure 2 is a block diagram of a voltage to time converter,

figure 3 illustrates an embodiment of a voltage to time converter,

figure 4 illustrates an embodiment of a boot strapped switch,

figure 5 illustrates the concept of input com mon-mode voltage range,

figure 6 illustrates the effect of level shift ing,

figure 7 illustrates level shifting with a ref erence voltage,

figure 8 illustrates reference-free level shifting,

figure 9 illustrates a ramp generator, figure 10 is a timing diagram of signals in the ramp generator of fig. 9,

figure 11 illustrates a ramp generator with an output-impedance-boosting inverter,

figure 12 is a timing diagram of signals in the ramp generator of fig. 11,

figure 13 illustrates an operating state of the voltage to time converter of fig. 3,

figure 14 illustrates another operating state of the voltage to time converter of fig. 3, and

figure 15 is a timing diagram of signals asso- crated with figs. 3, 13, and 14. DETAILED DESCRIPTION

Fig. 1 illustrates a general principle of using voltage to time conversion as a part of analog to digital conversion. A voltage to time converter 101, referenced to by the acronym VTC, has an input for an analog volt age. The VTC generates start and stop signals that go to a time to digital converter 102, referenced to by the acronym TDC. The start and stop signals may be any kind of signals, each of which defines at least one unequiv ocal moment of time. In many cases the start and stop signals are rising and/or falling edges of logic sig nals, such rising and falling edges being defined as transitions between two predetermined voltage levels.

The difference in time between the start and stop signals is proportional to the magnitude of the analog input voltage at a sampling moment or sampling interval. The exact definition of a sampling moment or sampling interval may depend on the actual implementa tion of the VTC. For many purposes it may be sufficient to assume that changes in voltage are slow enough in comparison to the sampling rate so that the difference in time between the start and stop signals represents a momentary value that the analog input voltage has at the time of producing that particular pair of start and stop signals. In other cases it may be defined that the dif ference in time between the start and stop signals rep resents an average value of the analog input voltage during the time interval between that particular pair of start and stop signals; or the value that the analog input voltage acquires at the exact moment of giving the stop signal; or others. For the discussion here the exact definition of a sampling moment or sampling in terval is not important, although the exemplary imple mentations described may favor some definitions more than others .

The role of the TDC 102 is to produce a sequence of digital values at its digital output, each digital value in the sequence indicating the length of time between the immediately preceding pair of start and stop signals from the VTC. The following discussion will con centrate on advantageous example implementations of the VTC 101, so it suffices to assume that some kind of a TDC is available and can be coupled to receive the start and stop signals and configured to produce the appro priate digital values.

Fig. 2 illustrates an example of a VTC 101, which comprises an input 201 for an analog voltage. The input 201 is drawn as a single line in fig. 2 for graph ical simplicity, but for reasons that will become evi dent below it is advantageous if the input 201 is a differential input with a first node and a second node for receiving an input voltage in the form of a potential difference between such first and second nodes. The VTC 101 comprises also a clock input 202 for receiving a clock signal CK. A sample and hold (S/H) circuit 203 is coupled to the (differential) input 201 for temporarily storing a sample of the input voltage. The storing is accomplished according to a sampling schedule defined by the clock signal CK. The clock signal CK is a periodic signal in which a certain regular waveform repeats over and over again with a certain duty cycle, i.e. a certain ratio between the proportional lengths of the high and low values. The sampling schedule may be defined for example so that a sample of the analog input voltage is taken during a high value of the clock signal waveform, and held for the duration of the subsequent low value of the clock signal waveform.

The VTC 101 of fig. 2 comprises a level shifter 204 coupled to the S/H circuit 203. The purpose of the level shifter 204 is to controllably shift a level of the stored sample to produce a level-shifted sample. The clock signal CK comes as an input not only to the S/H circuit 203 but also to the level shifter 204, which enables the last-mentioned to perform the level shifting in synchronism with the operation of the S/H circuit 203. The advantage gained through the use of a level shifter 204 will be more apparent later in this text. The VTC 101 of fig. 2 comprises a ramp generator 205 for generating a ramp voltage according to a conversion schedule. Also the conversion schedule is defined by the clock signal CK, because the generated ramp voltage is to be used in the evaluation of the stored samples. A comparator 206 is configured to compare the generated ramp voltage to a threshold and to output a stop signal STOP in response to the ramp voltage reaching the threshold. The ramp generator 205 is configured to use the level-shifted sample as an offset in generating the ramp voltage. This makes the timing of the stop signal STOP with reference to the clock signal CK dependent on the value of the level-shifted sample.

In the implementation shown in fig. 2 the start signal START comes through the VTC 101 as an inverted form of the clock signal CK. Since the clock signal CK is not generated internally in the VTC 101 but comes to it as an input, it would be possible to produce the start signal START without involving the VTC 101, for example simply by taking a branch from the clock signal line outside the VTC and using suitable inverters, buff ers, and/or other circuit elements to take it to a sub sequent TDC, which is not shown in fig. 2.

The functional blocks 203, 204, 205, and 206 of the VTC are shown separated from each other in fig. 2 for graphical clarity. As in many cases with microe lectronics it is not necessary to make such functional blocks completely separate from each other: one or more components of the actual circuit-level implementation may have a role in two or more functional blocks. An example of this is shown in fig. 3.

The VTC of fig. 3 comprises a differential in put 201, which here is explicitly shown to have a first node 301 and a second node 302. Through the differential input 201 the VTC of fig. 3 may receive an input voltage in the form of a potential difference between the first and second nodes 301 and 302. The potential difference is the difference of the input voltage values Vin+ and Vin- in fig. 3.

A clock input is not separately shown in fig. 3 for graphical clarity, but the effect of a clock signal CK on a number of switches is shown. The inverted clock signal is shown in the drawing with a line above the letters C and K, but in written text the form /CK can be used. The effect of the inverted clock signal /CK is shown in fig. 3 as well. The clock signal CK and the inverted clock signal /CK may both be received as input signals to the VTC, or one may be produced from the other with an inverter within the VTC.

The VTC of fig. 3 comprises a sample and hold circuit 203 coupled to the differential input 201. The sample and hold circuit 203 comprises a capacitor 317 as well as switches 308 and 309 that implement the cou pling to the differential input 201. The clock signal CK is shown to control the switches 308 and 309 so that they are conductive when the clock signal CK is high and non-conductive when the clock signal CK is low. In other words, the duration of time during which the clock sig nal CK is high constitutes a sampling interval, during which the differential input voltage charges the capac itor 317.

Advantageous sampling performance can be achieved by using bootstrapped switches as the switches 308 and 309. Without bootstrapping there might be input- dependent on-resistance in the switches, causing un wanted non-linearity in the sampling. Fig. 4 illustrates an example of a bootstrapped switch design that can be used. When the clock signal CK is low, the capacitor- coupled FET 401 is charged to VDD through FETs 402 and 403, while the potential of point 404 is kept at ground potential with FETs 405 and 406. When the clock signal CK is high, one terminal of the capacitor-coupled FET 401 is connected to the input through FET 407, whereas the other terminal is connected to the switch transistor 408 through FET 409. Consequently, the overdrive voltage VOV of the switch transistor 408 is maintained at VDD, even when the input voltage is changing. This way the impedance of the bootstrapped switch remains relatively constant, resulting in higher linearity compared to e.g. to transmission (Tx) gates.

Referring back to fig. 3, the VTC comprises a level shifter 204 that is coupled to the sample and hold circuit 203 for controllably shifting a level of the stored sample. Advantages can be gained by using a so- called reference-free level shifter that comprises a plurality of capacitances 303 and 304 and a correspond ing plurality of switches 305, 306, and 307 for con trollably connecting the capacitances 303 and 304 to respective constant potential rails of the VTC. In the embodiment of fig. 3 switch 305 can be used to connect a first terminal of capacitance 303 to the positive constant potential rail, switch 306 can be used to con nect a first terminal of capacitance 304 to the ground potential rail, and switch 307 can be used to connect a second terminal of both capacitances 303 and 304 to the ground potential rail.

This connecting is advantageously done accord ing to a level-shifting schedule defined by the clock signal CK. In the embodiment of fig. 3 switch 307 is conductive at a high value of the clock signal CK. Switches 305 and 306 are toggle switches so that at a high value of the clock signal CK they make the connec tion to the respective constant potential rail and at a low value of the clock signal CK they connect the first terminals of capacitances 303 and 304 together to one terminal of the capacitance 317 in the sample and hold circuit. This way the level-shifting schedule conforms with the sampling schedule: the switches 305, 306, and 307 are configured to controllably connect respective ones of the capacitances 303 and 304 to the constant potential rails in synchronism with the temporary stor ing of samples of input voltage in the sample and hold circuit 203.

The advantages of a reference-free level shifter are explained in the following with reference to figs. 5, 6, 7, and 8. Fig. 5 shows the levels of a positive constant potential VDD and a ground potential VSS as horizontal lines. The potential difference be tween VDD and VSS is the operating voltage of the VTC. This is also the range of input potential values that the VTC can correctly handle.

A differential input voltage consists of po tential variations around a common mode (CM) potential that is common to the both input nodes. The common mode potential is frequently called the common mode voltage, although exactly speaking the term voltage refers to a potential difference. If the common mode voltage would be at the level of VDD, one half of the input potential values (the highest values) would be clipped because they would be higher than VDD, as shown with the hatched area between curve 501 and the VDD line. Similarly if the common mode voltage would be at the level of VSS, one half of the input potential values (the lowest val ues) would be clipped because they would be lower than VSS, as shown with the hatched area between curve 502 and the VSS line. There is a certain range of potential values, called the constant mode voltage range (CMVR) , within which the common mode voltage must be in order to maintain all input potential variations between VSS and VDD.

More exactly, the input CMVR should be re stricted by

where Vi_n,_CM is the common mode voltage and V±_n,_peak is the largest difference between the potential of any of the input voltage nodes and the common mode voltage. A differential signal has one half of its swing on each side of the common mode voltage, so if the maximum peak-to-peak variation in the input voltage equals half of VDD (taken VSS = 0V) , the input common mode voltage range CMVR is from 0.25VDD to 0.75VDD.

A differential input signal to the circuit of fig. 3 has inherently its common mode voltage at 0V, with an amplitude that varies between +Vpeak and -Vpeak, as shown by curve 601 in fig. 6. Assuming that +Vpeak is in any case smaller than VDD and that VSS=0V, an example of successful level shifting is the one shown with the curve 602: here the original differential input signal has been linearly scaled and shifted so that its common mode voltage is at +Vpeak/2 and its amplitude varies between +Vpeak and 0V.

Fig. 7 illustrates the principle of a level shifter that is not reference-free but requires a ref erence voltage Vref. The left part of fig. 7 shows how, during a sampling period, a sampling capacitance C_s is coupled to the differential input voltage between Vin+ and Vin- while the level-shifting capacitance C_Ls is charged to the reference voltage Vref. The right part of fig. 7 shows how, after the sampling period, a level- shifted sample Vx is produced. If the capacitances C_s and C_Ls are equal, Vx is the mean value of Vin and Vref. In the more general case Vx is the weighted average of Vin and Vref, where the weights are the capacitance values .

Level shifting of the kind shown in fig. 6 can be made with a level shifter according to fig. 7. As suming that the capacitances are equal, this requires a low impedance positive reference voltage Vref of magni tude +Vpeak. A disadvantage of requiring a separate, accurate low-impedance voltage source is the resulting requirement of additional complexity, added power con sumption, and silicon area that must be allocated to the reference voltage generator. A reference voltage could be generated externally and brought to the VTC from outside, but this in turn requires additional contact pads and increases complexity and component count on the circuit board.

Fig. 8 shows an example of a reference-free level shifter. This principle is also applied in the circuit of fig. 3. The reference-free level shifter of fig. 8 comprise a plurality of (here: two) capacitances

802 and 803 and a corresponding plurality of switches. The switches are not separately shown in fig. 8, but examples of such switches can be seen as switches 305, 306, and 307 in fig. 3. The switches are used to con- trollably connect the plurality of capacitances 802 and

803 to respective constant potential rails of the VTC according to a level-shifting schedule defined by a clock signal. In the circuit of fig. 3 the clock signal is the clock signal CK. This way the level-shifting schedule conforms with the sampling schedule, so that the plurality of switches are configured to controllably connect respective ones of the capacitances 802 and 803 to the constant potential rails in synchronism with the temporary storing of samples of input voltage in the sample and hold circuit. In fig. 8 the sample and hold circuit is represented by the capacitance 801 on the left .

As shown in fig. 8, among the plurality of capacitances used for level shifting are a first capac itance 802 and a second capacitance 803. The left-hand part of fig. 8 shows a first phase of the level-shifting schedule, during which the plurality of switches (see switch 305 in fig. 3) are configured to controllably charge the first capacitance 802 to an operating voltage VDD of the VTC. Simultaneously the plurality of switches (see switches 306 and 307 in fig. 3) are configured to controllably charge the second capacitance 803 to a zero (ground) voltage. The right-hand part of fig. 8 shows a second phase of the level-shifting schedule, during which the plurality of switches (see switches 305, 306, and 318 in fig. 3) are configured to controllably con nect the first and second capacitances 802 and 803 to the sample and hold circuit for producing the level- shifted sample as a combination of the stored sample and the voltages to which the first and second capacitances 802 and 803 were charged.

If the first and second capacitors 802 and 803 are equal in value, connecting them together after the charging phase on the left in fig. 8 makes the combina tion acquire a voltage that is exactly half-way between VDD and 0V (in the more general case the voltage is the weighted average of VDD and 0V) . Connecting this combi nation to the sampling capacitor 801 performs the level shifting as shown in fig. 6 above. No separate reference voltages are needed, because the voltages VDD and 0V will be available in the VTC anyway, and the additional required silicon area is small in comparison to what would be needed if the approach of fig. 7 was used.

Fig. 9 illustrates an example of a ramp gener ator. The ramp generator of fig. 9 comprises a current source 901 that can be controllably coupled to a sample and hold capacitor 902. Switches 903 and 904 are used to controllably couple the sample and hold capacitor 902 to an input voltage (note the opposite polarity compared to fig. 3) on the high levels of a clock signal CK. Switches 905 and 906 are used to controllably couple the sample and hold capacitor 902 between the output of the current source 901 and the ground voltage on the high levels of the inverted clock signal /CK. Switch 907 is used to maintain the output of the current source 901 at the ground potential during high levels of the clock signal CK. The output of the ramp generator is the po tential marked as V_R in fig. 9. Fig. 10 shows examples of signals in the ramp generator of fig. 9 during slightly more than one clock cycle. While the clock signal CK is high, a sample of the input voltage is taken into the capacitor 902, while the output potential V_R remains zero. When the clock signal CK goes low and its inverse /CK goes high, the constant current produced by the current source 901 be gins to charge the capacitor 902. The voltage of the capacitor 902 does not (necessarily) begin from zero but from a level defined by the sample of the input voltage that was stored therein before the clock signal CK went low: this is illustrated with the dashed alternative courses of the rising ramp in V_R. Assuming that the output current of the current source 901 remains con stant and that also other nonlinearities of the circuit have been eliminated, the potential V_R increases line arly until the clock signal CK goes high again and the cycle begins anew.

Fig. 10 shows also how a comparison to a ref erence or threshold level V_REF can be used to produce an output signal (a STOP signal) when the potential V_R equals or exceeds the reference or threshold level V_REF: the STOP signal comes the earlier in the cycle, the larger was the magnitude of the sampled voltage.

Mathematically the ramp-like rising of the po tential V_R from Vin high enough to equal V_REF at time t_c can be expressed

V_R

where I_R is the current produced by the current source 901, R_R is the output impedance of the current source 901, and C_R is the value of the sample and hold capacitance 902. This expression can be solved for t_c as a function of Vin to give

A Taylor series expansion T up to the third order gives, after some condensing,

From this form it is apparent that a large output impedance R_R will minimize the higher-order terms and thus enhance linearity. In a ramp generator solution like that in fig. 9 it is thus advantageous to boost the output impedance of the current source 901.

One way of boosting the output impedance is to add an operational amplifier at the output of the ramp generator. However, taken the high speed requirements typical to VTC applications, an operational amplifier should have large bandwidth and exceptionally good lin earity. This means that it would easily consume large amounts of power and silicon area.

Fig. 11 illustrates an advantageous solution in which an inverter 311 is used as an impedance buffer to boost the output impedance of a current source 310. Many reference designators in fig. 11 are the same as in fig. 3 in order to emphasize the application of the solution of fig. 11 in the circuit of fig. 3. When the clock signal CK is high, a sample of the input voltage Vin is taken to the sample and hold capacitor 317. Switches 1101 and 1102 are driven with the inverted clock signal /CK, so during the sampling interval they keep the inverter 311 isolated from the sample and hold circuit. When the clock signal CK goes low and its in verse /CK goes high, the current source 310 begins to charge the sample and hold capacitor 317, the input voltage sample stored therein setting the starting level of the resulting voltage ramp as shown in fig. 12.

Employing an inverter 311 as the impedance buffer allows building the circuit with small power con sumption and small requirement of silicon area. Addi tionally it maintains the output common-mode of the ramp at the threshold level V_T of the inverter, eliminating the need of any differential comparator at the output of the ramp generator. A chain of inverters can be used to implement a function that essentially conforms with the comparator example of fig. 2. This explains why the chain of one or more inverters 314, 315, and 316 is marked with the reference designator 206 in fig. 3. The threshold voltage, which is marked with V_T in fig. 12, is an inversion threshold voltage of the chain of one or more inverters 314, 315, and 316.

Figs. 13 and 14 illustrate the two phases of operation of the VTC of fig. 3, corresponding to the high value of the clock signal CK (fig. 13) and the low value of the clock signal CK (fig. 14) . An example of some signal waveforms is shown in fig. 15. These draw ings can also be examined as illustrating a method for performing voltage to time conversion. Switches that are conductive are shown as just continuous lines in figs. 13 and 14, while switches that are non-conductive are shown with the usual symbol of a switch.

In fig. 13 the switches 312, 313, and 318 are non-conductive, and the switches 305 and 306 connect the respective ones of the plurality of capacitances 303 and 304 to the respective constant potential rails. This is the sampling period, corresponding to a method step of temporarily storing a sample of a differential input voltage that appears between the input nodes 301 and 302. This temporary storing is accomplished according to a sampling schedule defined by the clock signal CK. In fig. 15 this is the period between moments 1501 and 1502.

As shown in fig. 13, using the exemplary level shifter architecture explained above with reference to fig. 8, the sampling period comprises connecting one 303 of the plurality of capacitances to an operating voltage of the VTC and connecting another 304 of the plurality of capacitances to a zero voltage.

The output of the current source 310 is con nected to ground in fig. 13, corresponding to the switch 319 (see fig. 3) being conductive. Allowing current from the current source 310 to escape to ground this way might be considered a waste of energy, and avoiding it could save some power. However, on one hand the current generated by the current source 310 is relatively small and the relative duration of the sampling period may be quite short, so the associated waste of electric energy is not that large. And on the other hand, keeping the current source 310 constantly active helps to ensure stability of the amount of electric current it produces. For these reasons it is considered to be an acceptable solution to have the output of the current source 310 connected to ground for the duration of the sampling interval 1501-1502.

In fig. 14 the (advantageously bootstrapped) sampling switches 308 and 309 become non-conductive, marking the end of the sampling interval. The moment of flipping the switches 305 and 306 to the position shown in fig. 14 represents shifting a level of the stored sample, to produce a level-shifted sample. In particu lar, the level-shifting comprises connecting each of the plurality of capacitances 303 and 304 together into com bination with the sample stored in capacitance 317, ac cording to a level-shifting schedule defined by the (falling edge of the) clock signal CK.

This moment also marks the beginning of gener ating a ramp voltage according to a conversion schedule defined by the clock signal CK. It comprises using the level-shifted sample as an offset in generating the ramp voltage. In fig. 14 it is seen how the current source 310 now begins to charge the capacitance 317, so that the magnitude of the level-shifted sample constitutes said offset. In fig. 15 it is seen how the input voltage (represented by the curve 1503) had a moderately large positive value, causing an offset 1504 to the point at which the ramp voltage begins at moment 1502.

The slope of the ramp is constant, defined es sentially by the magnitudes of the output current of the current source 310 and the value of the capacitances 303, 304, and 317. In particular, the slope of the ramp does not depend on the magnitude of the offset 1504. The period during which the ramp voltage proceeds corre sponds to the method step of comparing the generated ramp voltage to a threshold. In this case the threshold is the inversion threshold voltage of the chain of one or more inverters between the output of the current source 310 and the output of the VTC, where the STOP signal will appear.

At moment 1505 in fig. 15 the ramp voltage reaches the threshold V_T . As seen in the lower part of fig. 15 the method comprises outputting a stop signal (i.e. generating a rising edge in the signal labeled STOP) in response to the ramp voltage reaching the threshold. Fig. 14 shows how the comparing of the gen erated ramp voltage to the threshold comprises inputting the generated ramp voltage to a chain of one or more inverters so that said threshold is an inversion thresh old voltage of said chain of one or more inverters.

The three cycles shown in fig. 15 illustrate how the offset in the ramp voltage makes timing of the stop signal with reference to the clock signal CK de pendent on the value of the level-shifted sample. Namely, at moment 1506 when the next sampling interval ends, the input voltage has an even larger positive value than at moment 1502, causing the offset in the ramp voltage to be very small. For this reason it takes a longer time, up to moment 1507, before the ramp voltage reaches the threshold. Consequently the time interval between the preceding rising edge in the clock signal CK and the rising edge in the stop signal at moment 1507 is longer than that between moments 1501 and 1505. When the third sampling interval in fig. 15 ends at moment 1508, the input voltage has a relatively large negative value, causing the offset in the ramp voltage to be large. Consequently there will be only a short time interval before the ramp voltage reaches the threshold at moment 1509.

A method for performing analog to digital con version may comprise using any of the method embodiments explained above to perform analog to time conversion, and using a method of time to digital conversion to convert into digital form a detected length of time between the stop signal and a preceding start signal. A the start signal it is possible to use a rising edge and/or a falling edge of the clock signal CK that also defines the sampling, level shifting, and conversion schedules in the VTC.

Those skilled in the art should understand that each block or step of the methods disclosed herein, or any combinations of the blocks or steps, can be imple mented by various means, such as hardware, firmware, and/or software. As an example, one or more of the blocks or steps described above can be embodied by computer executable instructions, data structures, program mod ules, and other suitable data representations. Further more, the computer executable instructions which embody the blocks or steps described above can be stored on a corresponding data carrier and executed by at least one processor. This data carrier can be implemented as any computer-readable storage medium configured to be read able by said at least one processor to execute the com puter executable instructions. Such computer-readable storage media can include both volatile and nonvolatile media, removable and non-removable media. By way of ex ample, and not limitation, the computer-readable media comprise media implemented in any method or technology suitable for storing information. In more detail, the practical examples of the computer-readable media in clude, but are not limited to information-delivery me dia, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile discs (DVD) , hol ographic media or other optical disc storage, magnetic tape, magnetic cassettes, magnetic disk storage, and other magnetic storage devices.

Although the exemplary embodiments of the pre sent disclosure are described herein, it should be noted that any various changes and modifications could be made in the embodiments of the present disclosure, without departing from the scope of legal protection which is defined by the appended claims. In the appended claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. Voltage to time converter, hereinafter VTC, comprising:

- a differential input (201) with a first node (301) and a second node (302), for receiving an input volt age in the form of a potential difference between said first and second nodes (301, 302),

- a clock input (202) for receiving a clock signal (CK) ,

- a sample and hold circuit (203) coupled to said dif ferential input (201) for temporarily storing a sample of said input voltage according to a sampling schedule defined by said clock signal (CK) ,

- a level shifter (204) coupled to said sample and hold circuit (203) for controllably shifting a level of the stored sample to produce a level-shifted sam ple,

- a ramp generator (205) for generating a ramp voltage according to a conversion schedule defined by said clock signal (CK) , and

- a comparator (206) configured to compare the gener ated ramp voltage to a threshold and to output a stop signal (STOP) in response to said ramp voltage reach ing said threshold;

wherein said ramp generator (205) is configured to use said level-shifted sample as an offset in generating said ramp voltage.

2. The VTC of claim 1, wherein the VTC is configured to make a timing of said stop signal (STOP) with reference to said clock signal (CK) dependent on a value of said level-shifted sample.

3. The VTC of claim 1 or 2, wherein said level shifter (204) is a reference-free level shifter that comprises a plurality of capacitances (303, 304) and a corresponding plurality of switches (305, 306, 307) for controllably connecting said plurality of ca pacitances (303, 304) to respective constant potential rails of said VTC according to a level-shifting sched ule defined by said clock signal (CK) .

4. The VTC of claim 3, wherein said level- shifting schedule conforms with said sampling schedule so that said plurality of switches (305, 306, 307) are configured to controllably connect respective ones of said plurality of capacitances (303, 304) to said con stant potential rails in synchronism with said tempo rary storing of samples of input voltage in said sam ple and hold circuit (203) .

5. The VTC of claim 3 or 4, wherein:

- said plurality of capacitances (303, 304) comprise a first capacitance (303) and a second capacitance

(304) ,

- said plurality of switches (305, 306, 307) are con figured to controllably charge said first capacitance (303) to an operating voltage of the VTC and said sec ond capacitance (304) to a zero voltage according to said level-shifting schedule,

- said plurality of switches (305, 306, 307, 318) are configured to controllably connect said first and sec ond capacitances (303, 304) to said sample and hold circuit (203) according to said level-shifting sched ule, for producing said level-shifted sample as a com bination of said stored sample and the voltages to which said first and second capacitances (303, 304) were charged.

6. The VTC of any of the preceding claims, wherein said sample and hold circuit (203) comprises bootstrapped switches (308, 309) that implement said coupling to said differential input (201) .

7. The VTC of any of the preceding claims, wherein said ramp generator (205) comprises a current source (310), and an impedance buffer (311) at an out put of said current source (310) for boosting an out put impedance of said current source (310) .

8. The VTC of claim 7, wherein said ramp gen erator (205) comprises one or more conversion switches (312, 313) for controllably forming a capacitive feed back coupling across said impedance buffer (311) through said sample and hold circuit (203) and said level shifter (204) according to said conversion schedule .

9. The VTC of any of claims 7 or 8, wherein said impedance buffer (311) is an inverter.

10. The VTC of any of the preceding claims, wherein said comparator (206) comprises a chain of one or more inverters (314, 315, 316), so that said threshold is an inversion threshold voltage of said chain of one or more inverters (314, 315, 316) .

11. Analog to digital converter, comprising:

- a VTC according to any of claims 1 to 10, and

- a time to digital converter coupled to said VTC to receive said stop signal (STOP) from said VTC and con figured to convert into digital form a detected length of time between said stop signal (STOP) and a preced ing start signal (START) .

12. The analog to digital converter of claim 11, wherein:

- said VTC is configured to deliver said clock signal in at least one of a direct or inverted form as said start signal to said time to digital converter.

13. Method for performing voltage to time conversion, comprising: - temporarily storing a sample of a differential input voltage according to a sampling schedule defined by a clock signal (CK) ,

- shifting a level of the stored sample to produce a level-shifted sample,

- generating a ramp voltage according to a conversion schedule defined by said clock signal (CK) ,

- using said level-shifted sample as an offset in gen erating said ramp voltage,

- comparing the generated ramp voltage to a threshold, and

- outputting a stop signal (STOP) in response to said ramp voltage reaching said threshold.

14. The method of to claim 13, wherein said offset in said ramp voltage makes timing of said stop signal (STOP) with reference to said clock signal (CK) dependent on a value of said level-shifted sample.

15. The method of claim 13 or 14, wherein said shifting of the level of the stored sample com prises alternately connecting each of a plurality of capacitances (303, 304) to:

- respective constant potential rails and

- together into combination with the stored sample; according to a level-shifting schedule defined by the clock signal (CK) .

16. The method of claim 15, wherein said con necting of each of said plurality of capacitances (303, 304) to respective constant potential rails com prises :

- connecting one (303) of said plurality of capaci tances (303, 304) to an operating voltage of the volt age to time converter performing said voltage to time conversion, and

- connecting another (304) of said plurality of capac itances (303, 304) to a zero voltage.

17. The method of any of claims 13 to 16, wherein said comparing of the generated ramp voltage to said threshold comprises inputting the generated ramp voltage to a chain of one or more inverters (314, 315, 316) so that said threshold is an inversion threshold voltage of said chain of one or more invert ers (314, 315, 316) .

18. Method for performing analog to digital conversion, comprising:

- using the method of any of claims 13 to 17 to per form analog to time conversion, and

- using a method of time to digital conversion to con vert into digital form a detected length of time be tween said stop signal (STOP) and a preceding start signal (START) .

19. The method of claim 18, comprising using at least one of a rising edge and a falling edge of said clock signal (CK) as said start signal.