JPS62188249A - Pin grid array package - Google Patents
Pin grid array packageInfo
- Publication number
- JPS62188249A JPS62188249A JP2982186A JP2982186A JPS62188249A JP S62188249 A JPS62188249 A JP S62188249A JP 2982186 A JP2982186 A JP 2982186A JP 2982186 A JP2982186 A JP 2982186A JP S62188249 A JPS62188249 A JP S62188249A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- printed circuit
- semiconductor element
- circuit board
- circuit pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000002356 single layer Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 229920005989 resin Polymers 0.000 claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 13
- 229920005992 thermoplastic resin Polymers 0.000 abstract description 9
- 238000000465 moulding Methods 0.000 abstract description 6
- 230000017525 heat dissipation Effects 0.000 abstract description 4
- 239000003365 glass fiber Substances 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 14
- 239000000919 ceramic Substances 0.000 description 10
- 239000010410 layer Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000003860 storage Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 244000062793 Sorghum vulgare Species 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 235000019713 millet Nutrition 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 235000011962 puddings Nutrition 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はＰＧＡ （ビングリッドアレイ）パッケージに
係り、特に、中層構造体のＰＧΔパッケージの改良に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a PGA (Bing Grid Array) package, and more particularly to an improvement of a PGΔ package of an intermediate structure.
ＰＧＡパッケージとしては、従来から、多層または単層
セラミック基板、多層または単層プリント基板などを用
いたものが知られているが、このうち多層セラミック基
板１を用いたＰＧＡパッケージは、第６図に示すように
、多層セラミック基板１に半導体素子（図示せず）を収
容するための半導体素子収納穴２を形成し、この半導体
素子収納穴２内に内側先端部に半導体素子とワイＸ７（
図示Ｖず）により結線するためのワイヤホンディング領
域を有する導体回路パターン３を形成するとともに、多
層セラミック基板１に複数本のり−ドピン５．５・・・
を植設して構成されているが、このＰＧＡパッケージは
コストが高いという問題点を右していた。また、多層プ
リンｌ−ｊＪ板６を用いた第７図のＰＧＡパッケージは
、多層プリンｌ−基１反６に形成した半導体素子収納穴
２内に内端部にワイヤボンディング領域を右する導体回
路パターン３を形成でるとと６に、多層プリン１一基板
６に複数本のリードピン５．５・・・を植設し、かつ多
層ブリント基板６０表面に放熱用のヒートシンク７を張
設して構成されているが、プリントＬ（板を用いたＰ
Ｇ Ａパッケージは、ガラス織前などを合む樹脂からな
る板体を用いる！こめ、外側の樹脂およびガラス繊維間
の界面や、積層した板体間の間隙から半導体素子収納穴
２内に湿気などが入りやすく、導体回路や半４（Ａ素子
に悪影響を与え（Ｇ頼性に欠（ノる問題点を有していた
。さらに、積層したプリン１− ｘ、を板の全体もしく
は部分的に剥離が発生しやすく、しかもその検出は困難
であるため製造工程上の管理に細心の注意を払られなけ
ればらなかった。さらにまた、プリント基板を用いたパ
ッケージにＪ３いては、各リードピン５を植設するため
プリン１〜基板にスルーホールを形成し、このスルーボ
ール内に金属皮膜を形成しなければならないため、作業
性が悪かった。また、単層の基板を用いたバック°−ジ
では、゛Ｉｆ−導体素子を収容するための凹部を基板に
形成しなければならなかった。Conventionally, PGA packages using multilayer or single-layer ceramic substrates, multilayer or single-layer printed circuit boards, etc. are known. As shown, a semiconductor element storage hole 2 for accommodating a semiconductor element (not shown) is formed in a multilayer ceramic substrate 1, and a semiconductor element and a wire X7 (
A conductive circuit pattern 3 having a wire bonding area for connection is formed using a wire bonding area (not shown), and a plurality of bonded pins 5, 5... are formed on the multilayer ceramic substrate 1.
However, this PGA package had the problem of high cost. In addition, the PGA package shown in FIG. 7 using the multilayer printed circuit board 6 has a conductor circuit with a wire bonding area at the inner end inside the semiconductor element storage hole 2 formed in the multilayer printed circuit board 6. After forming the pattern 3, a plurality of lead pins 5, 5, etc. are implanted in the multilayer printed circuit board 1 and the printed circuit board 6, and a heat sink 7 for heat dissipation is stretched on the surface of the multilayer printed circuit board 60. However, print L (P using a board)
GA package uses a plate made of resin with glass woven fabric etc. Therefore, moisture easily enters the semiconductor element storage hole 2 from the interface between the outer resin and glass fibers and the gap between the laminated plates, which has a negative effect on the conductor circuit and half 4 (A element). In addition, the laminated pudding 1- Careful attention had to be paid to the J3 package using a printed circuit board.In order to implant each lead pin 5, through holes were formed in the printed circuit board 1 and the board, and metal was inserted into the through balls. Workability was poor because a film had to be formed.Furthermore, in backges using single-layer substrates, it was necessary to form recesses in the substrate to accommodate the If-conductor elements. Ta.
ざらに最近では、半導体素子の高集積化に伴って素子も
大ｊｌ＋７になり、半導体素子取付は面の面積を広く必
要どするため、この而の平ｊ口度を良好に確保すること
ら困テ「になってきた。In recent years, as semiconductor devices have become more highly integrated, the size of the devices has increased to Jl+7, and mounting semiconductor devices requires a large surface area, making it difficult to ensure a good level of flatness. Te: “It has become.
本発明は、＋ｉｆｆ述した点に鑑み、耐湿性が良好で、
しかも作業性よく安価に製造でさるＰ Ｇ Ａパッケー
ジを提供することを目的とする。In view of the points mentioned above, the present invention has good moisture resistance,
Moreover, it is an object of the present invention to provide a PGA package that is easy to work with and can be manufactured at low cost.
（発明の概要）
本発明は、導体回路パターンが形成され複数本のリード
ピンを突設しでなる゛Ｙ導体素子取イ１け而の先端部が
外部に露出するように樹脂にＪ：り被覆し、かつヒート
シンクよｌこは該樹脂が半導体素子取付ｉＪ面を形成す
るようにモールド成形したことを特徴としている。(Summary of the Invention) The present invention provides a Y conductor element having a conductor circuit pattern formed thereon and having a plurality of lead pins protruding from it. Moreover, the heat sink side is characterized in that the resin is molded so as to form a semiconductor element mounting surface.
（発明の実施例〕
以下、本発明を図面に示す実施例により説明する。なお
、前述した従来のものと同一の構成については、図面中
に同一符号を付し、（の説明は省略する。(Embodiments of the Invention) The present invention will be described below with reference to embodiments shown in the drawings.The same components as those of the prior art described above are denoted by the same reference numerals in the drawings, and the explanation thereof will be omitted.
第１図の左十図は本発明に係るＰＧＡパッケージの実施
例を示すものであり、ガラス繊維などを含む樹脂からな
る単層プリント基板８には間口９が形成されて４３す、
この間口９の内側面は破断面の耐湿性を向上させるため
樹脂１１により被覆されている。また、前記単層プリン
１−基板８の下面には導体回路パターン３が形成されて
おり、内側先端部は半導体素子（図示せず）どワイヤ（
図示けず）により結線するだめのワイヤボンディング領
域と／、１っている。この導体回路パターン３と連通ず
る複数本のリードピン５．５・・・が突没されている。Fig. 10 on the left of Fig. 1 shows an embodiment of the PGA package according to the present invention, in which a single-layer printed circuit board 8 made of resin containing glass fiber or the like has an opening 9 formed therein.
The inner surface of this opening 9 is coated with resin 11 to improve the moisture resistance of the fractured surface. Further, a conductive circuit pattern 3 is formed on the lower surface of the single-layer printed circuit board 1-substrate 8, and the inner tip portion is connected to a semiconductor element (not shown) or a wire (
(not shown) with a wire bonding area for connection. A plurality of lead pins 5, 5, . . . communicating with the conductive circuit pattern 3 are protruded and recessed.
そして、このように（ｊ４成された中層プリント１；モ
仮８の外周【９１導体回路パターン３の内端部のワイヤ
ボンディング領域を除さ熱可塑性樹脂１１によりヒート
シンク（放熱板）７どと乙に一体にモールド成形されて
いる。なお、前記熱可塑性樹脂１１の間口１２の周縁に
【４Ｌ突起１３庖周設することにＪこり、半導体（；子
搭載後にこの突起１３に当接ざけてギャップ４を接合さ
せることにより熱ｎ１塑性樹脂１１の間口１２を閉塞さ
せる気密封止の信頼性を高めることができる。Then, the outer periphery of the printed middle layer 8 [91] except for the wire bonding area at the inner end of the conductor circuit pattern 3, the heat sink (heat sink) 7 and It should be noted that it is difficult to provide a 4L protrusion 13 on the periphery of the opening 12 of the thermoplastic resin 11; By joining 4, it is possible to improve the reliability of the airtight seal that closes the opening 12 of the thermoplastic resin 11.
このようなＰＧＡパッケージを装造するにｔま、まず、
第２図のも半回に示すように、単層プリント基板８の導
体回路パターン３に連通ずるようにスルーホール１４に
複数本のリードピン５．５・・・をはんだイ」け、導電
性接着剤、圧入などにより接合する。その後、このリー
ドピン５を植設した単層プリント基板８を図示しないモ
ールド金型内でヒートシンク７とと６に熱可塑性樹脂１
１により樹脂モールドする。なお、このヒートシンク７
は必ずしも設置Ｊなくとｂよい。このモールド成形は、
ビー１−シンク７または熱可塑性樹脂１１が半導体素子
の取イ」け而を形成するようにする。なおこの際、半導
体素子の取付は位置の規制を［−ルド樹脂により行わせ
るどＪ：い。さらに中層プリント基板８に形成されたリ
ードピン５取イ・１け用のスルーホール１４内にははｌ
υだ皮膜や金めっきなどの表面処理１５を施しておくの
が望ましい。Before assembling such a PGA package, first,
As shown in the second half of FIG. 2, a plurality of lead pins 5. Join by using adhesive, press-fitting, etc. Thereafter, the single-layer printed circuit board 8 with the lead pins 5 implanted therein is placed in a mold (not shown) on the heat sinks 7 and 6 using thermoplastic resin 1.
1. Resin molding is performed. In addition, this heat sink 7
does not necessarily have to be installed. This molding is
The bead 1-sink 7 or the thermoplastic resin 11 forms the interface for the semiconductor element. At this time, the position of the semiconductor element should be regulated using a molded resin. Furthermore, in the through hole 14 for 5 lead pins and 1 lead pin formed in the middle layer printed circuit board 8, there is a l.
It is desirable to apply a surface treatment 15 such as a υ layer or gold plating.
このにうな第１図のＰＧＡパッケージは、プリント基板
８が単層であるため低コスト化をはかることができるば
かりでなく、熱可塑性樹脂１１の被覆ににり良好な耐２
性をうろことができ、しかもヒートシンク７により放熱
性も良好に確保することができる。This PGA package shown in FIG. 1 has a single-layer printed circuit board 8, which not only enables cost reduction, but also has good resistance to 2.
Furthermore, the heat sink 7 can ensure good heat dissipation.
なお、本発明に係るＰＧΔパッケージは、前述した中層
プリント基板８に限られるものでなく、単層のセラミッ
ク基板、金属板や箔からなる基体にガラス質成分などの
絶縁体を被覆して導体回路かつ半導体素子取付は面を具
備しない中層の基板を複数枚積層して、さらに高密度化
を図るものは複層となるが、これらもψ層構造体に含め
るものとづる。Note that the PGΔ package according to the present invention is not limited to the above-mentioned middle-layer printed circuit board 8, but is also a conductor circuit formed by covering a base made of a single-layer ceramic substrate, a metal plate, or a foil with an insulator such as a glassy component. In addition, semiconductor elements are mounted by laminating a plurality of intermediate layer substrates without surfaces, and multi-layered substrates are used to achieve higher density, but these are also considered to be included in the ψ layer structure.
第２図の左手図は、単層セラミック基板８Δの導体回路
パターン３にリードピン５．５・・・を接続する構成を
承り。各リードピン５は単層セラミック基板８△に形成
した導体回路パターン３のパッド部にろう句けされてい
る。この場合のＰＧＡパッケージの実施例を第１図の右
゛１−図に示す。このように１１１層プリン１一基板８
、重層セラミック基板８Ａなどの単ＦＪ ’ｔ：？＋
造林を用いたＰＧ△パッケージの場合、従来必要とされ
た半導体素子取付けのための四部を基板に形成すること
が不要どなるうえ、直接ヒートシンクを一体にモールド
成形できるため放熱効果も良好でプリントＬｔ板８、セ
ラミック基板８△をｉ＃Ｉ７覆している熱可塑性樹脂１
１は外部からの衝撃に対し１４板を保ａすることかでき
ろ。The left-hand view in FIG. 2 shows a configuration in which lead pins 5, 5, . . . are connected to the conductor circuit pattern 3 of the single-layer ceramic substrate 8Δ. Each lead pin 5 is soldered to a pad portion of a conductive circuit pattern 3 formed on a single-layer ceramic substrate 8Δ. An example of the PGA package in this case is shown in FIG. In this way, 111 layers 1 board 8
, a single FJ such as a multilayer ceramic substrate 8A:? +
In the case of the PG△ package using afforestation, it is no longer necessary to form four parts on the board for attaching semiconductor elements, which was required in the past, and the heat sink can be directly molded into one piece, so the heat dissipation effect is good and the printed Lt board can be used. 8. Thermoplastic resin 1 covering i#I7 over ceramic substrate 8△
1 can protect 14 plates from external impact.
なお、前述した第１図の実施例においては、いわゆる４
ニヤビテイダウン型のもの（二ついて説明したが、第３
図に示すように、いわゆるキャビティアップ型のものと
しても同様の効果を秦することができる。また、リード
ピン５の接続り法としては、前述したように熱可塑性樹
脂１１ににるモールド成形前にリードピン５を単層プリ
ン１〜基板８に接続したが、第４図おＪ：び第５図に示
すように、このモールド成形時に熱可塑性樹脂１１に孔
１６を形成しておき、モールド成形後にリードピン５を
孔１６内に圧入または導ｍｆｌ接着剤などにより接合し
て導体回路パターン３との導通をはかることもできる。In addition, in the embodiment shown in FIG. 1 described above, so-called 4
Near-bite down type (I explained that there are two, but the third
As shown in the figure, a similar effect can be obtained using a so-called cavity-up type. As for the method of connecting the lead pins 5, as described above, the lead pins 5 were connected to the single layer print 1 to the substrate 8 before molding the thermoplastic resin 11. As shown in the figure, a hole 16 is formed in the thermoplastic resin 11 during molding, and after the molding, the lead pin 5 is press-fitted into the hole 16 or bonded with a conductive MFL adhesive or the like to connect it to the conductor circuit pattern 3. Continuity can also be measured.
この場合、ｔｔｉｌｉ１Ｍプリント旦板８のスルーホー
ル１４との接続を確実にするため高周波加熱などにより
リードピン５のみを高温にし、スルーホール１４内に形
成したはんだなどの金属皮膜やリードピンの接合個所に
予め被着した金属皮膜を溶融さＩて接続することも可能
である。このようにすると、リードピン５の接合がガス
タイト状となり、リードピン５の確実な接続が可能でリ
ードピン取付ｃ）部は良好な耐湿性を１ｑることができ
る。In this case, in order to ensure the connection with the through hole 14 of the ttili 1M printed board 8, only the lead pin 5 is heated to high temperature by high frequency heating etc., and the metal film such as solder formed in the through hole 14 or the joint location of the lead pin is pre-heated. It is also possible to connect by melting the deposited metal film. In this way, the connection of the lead pins 5 becomes gas-tight, the lead pins 5 can be connected reliably, and the lead pin attachment part c) can have good moisture resistance.
以上説明したように、本発明に係るＰＧΔパッケージは
、導体回路パターンが形成され複数本のリードピンを突
設してなる単層構造体の少なくとし導体回路パターンの
ワイＸ７ボンデイング領１或を除く外周を前記リードピ
ンの先端部が外部に露出するにうに！：Ａ脂により被覆
し、゛４ツ導体素子取イ」け面を一体にモールド成形ザ
るようにしたので、簡単な構成にらかかわらず良好な耐
湿性や平坦な半導体素子取付は面を得ることができ、ま
た伯粟性よく安価に製造できるという優れた効果を奏す
る。As explained above, the PGΔ package according to the present invention has a single-layer structure in which a conductor circuit pattern is formed and a plurality of lead pins protrude from the outer periphery of the conductor circuit pattern except for the YX7 bonding area 1. Make sure that the tip of the lead pin is exposed to the outside! :The surfaces for mounting the four conductor elements are coated with A resin and molded in one piece, so despite the simple structure, it has good moisture resistance and a flat surface for mounting the semiconductor elements. It also has the excellent effect of being able to be manufactured at low cost with good millet properties.
第１図は本発明に係るＰＧΔパッケージの実施例を示す
断面図、第２図は第１図のＰＧＡパッケージの製造工程
におりる中間段階を承り断面図、第３図は本発明の他の
実施例を示？ｌ−断面図、第４図および第５図はそれぞ
れリードピンの接続方法の他の実施例を示す要部の断面
図、第６図および第７図はそれぞれ従来のＰＧＡパッケ
ージを示す断面図である。
１・・・多層セラミック基板、３・・・導体回路パター
ン、４・・・二１ニヤツブ、５・・・リードピン、６・
・・多り月プリント基板、７・・・ビー１ヘシンク、８
・・・単層プリント基板、８Ａ・・・中層セラミック基
板、１１・・・熱可塑性樹脂、１４・・・スルー１１・
−ル。
第 ３ 図
第 ６ 図
第 ７ 図
１５８１讐す 昭和６１年６月９日 差Ｂ昭和６１年４
月 ２日
昭和６１年 特許願第２９８２１号
２、発明の名称
１） Ｇ Ａパッケージ
３、補圧をする者
π件との関係 特許出願人
４、代理人FIG. 1 is a sectional view showing an embodiment of the PGΔ package according to the present invention, FIG. 2 is a sectional view showing an intermediate step in the manufacturing process of the PGA package shown in FIG. Show examples? 4 and 5 are cross-sectional views of main parts showing other embodiments of the lead pin connection method, and FIGS. 6 and 7 are cross-sectional views showing conventional PGA packages, respectively. . DESCRIPTION OF SYMBOLS 1...Multilayer ceramic board, 3...Conductor circuit pattern, 4...21 pin, 5...Lead pin, 6...
・Tarizuki printed circuit board, 7...Be 1 hesink, 8
... Single layer printed circuit board, 8A ... Middle layer ceramic board, 11 ... Thermoplastic resin, 14 ... Through 11.
-L. Figure 3 Figure 6 Figure 7 Figure 1581 June 9, 1985 Difference B 4, 1986
May 2, 1986 Patent Application No. 29821 2, Title of the Invention 1) G A Package 3, Relationship with the person performing pressure compensation Patent Applicant 4, Agent
Claims (1)
突設してなり半導体素子取付け面を具備しない単層構造
体の少なくとも前記導体回路パターンの内端部を除く外
周を前記リードピンの先端部が外部に露出するように樹
脂により被覆し、かつヒートシンクまたは該樹脂が半導
体素子取付け面を形成するようにモールド成形したこと
を特徴とするＰＧＡパッケージ。A conductor circuit pattern is formed, a plurality of lead pins are protruding from the single layer structure, and the semiconductor element mounting surface is not provided. A PGA package characterized in that the PGA package is coated with a resin so as to be exposed and is molded so that the resin forms a heat sink or a semiconductor element mounting surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2982186A JPS62188249A (en) | 1986-02-13 | 1986-02-13 | Pin grid array package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2982186A JPS62188249A (en) | 1986-02-13 | 1986-02-13 | Pin grid array package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62188249A true JPS62188249A (en) | 1987-08-17 |
Family
ID=12286687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2982186A Pending JPS62188249A (en) | 1986-02-13 | 1986-02-13 | Pin grid array package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62188249A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0829097A4 (en) * | 1995-05-26 | 1999-04-14 | Hestia Technologies Inc | Method of transfer molding electronic packages and packages produced thereby |
| US6155642A (en) * | 1998-07-02 | 2000-12-05 | Oohiro Works, Ltd. | Barber/beauty chair |
| KR100479913B1 (en) * | 1997-09-10 | 2005-06-16 | 삼성테크윈 주식회사 | Pga package |
-
1986
- 1986-02-13 JP JP2982186A patent/JPS62188249A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0829097A4 (en) * | 1995-05-26 | 1999-04-14 | Hestia Technologies Inc | Method of transfer molding electronic packages and packages produced thereby |
| KR100479913B1 (en) * | 1997-09-10 | 2005-06-16 | 삼성테크윈 주식회사 | Pga package |
| US6155642A (en) * | 1998-07-02 | 2000-12-05 | Oohiro Works, Ltd. | Barber/beauty chair |
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