JPS62188144U - - Google Patents
Info
- Publication number
- JPS62188144U JPS62188144U JP7649686U JP7649686U JPS62188144U JP S62188144 U JPS62188144 U JP S62188144U JP 7649686 U JP7649686 U JP 7649686U JP 7649686 U JP7649686 U JP 7649686U JP S62188144 U JPS62188144 U JP S62188144U
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- bonded
- thickness
- semiconductor
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000008188 pellet Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案に係るハイブリツドＩＣの一実
施例を示す斜視図、第２図は第１図の断面図、第
３図は第２図の要部拡大断面図、第４図は本考案
の他の実施例を示す要部拡大断面図である。第５
図は従来のハイブリツドＩＣを示す斜視図、第６
図は第５図の断面図、第７図は第６図の要部拡大
断面図である。 １……リードフレーム、２……ランド部、８ａ
，８ｂ……半導体ペレツト、１３，１３′……配
線基板、１４……配線パターン、ｍ３……被ボン
デイング部位。
施例を示す斜視図、第２図は第１図の断面図、第
３図は第２図の要部拡大断面図、第４図は本考案
の他の実施例を示す要部拡大断面図である。第５
図は従来のハイブリツドＩＣを示す斜視図、第６
図は第５図の断面図、第７図は第６図の要部拡大
断面図である。 １……リードフレーム、２……ランド部、８ａ
，８ｂ……半導体ペレツト、１３，１３′……配
線基板、１４……配線パターン、ｍ３……被ボン
デイング部位。
Claims (1)
- 【実用新案登録請求の範囲】 導電性の配線パターンを形成すると共に、この
配線パターン上に、厚みの異なる複数種の半導体
ペレツトをマウントした配線基板を、リードフレ
ームのランド部上に固着してワイヤボンデイング
したハイブリツドＩＣにおいて、 上記配線パターンの被ボンデイング部位の膜厚
を、半導体ペレツトの厚さに対応させて厚くした
ことを特徴とするハイブリツドＩＣ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7649686U JPS62188144U (ja) | 1986-05-21 | 1986-05-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7649686U JPS62188144U (ja) | 1986-05-21 | 1986-05-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62188144U true JPS62188144U (ja) | 1987-11-30 |
Family
ID=30923629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7649686U Pending JPS62188144U (ja) | 1986-05-21 | 1986-05-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62188144U (ja) |
-
1986
- 1986-05-21 JP JP7649686U patent/JPS62188144U/ja active Pending