JPS62187954A - Bus control system - Google Patents

Abstract

PURPOSE:To prevent the change of the logic level of a bus from being delayed from a bus use complemention point by a bus master by forming a gate for setting up the logic of the bus to '1' during all bus masters possess no bus occupation right. CONSTITUTION:When a bus master 2 completes the use of a bus 5 and turns an enable signal outputted from a terminal A from '1' to '0', the output impedance of a try state 6 is turned to high impedance. Since all enable signals of bus masters 3-N are '0', the output of a NOR circuit 9 in a defining circuit 8 is changed from '0' to '1' and the output impedance of a try state 10 is turned to low impedance, so that current is conducted into the bus 5 and the potential of the bus 5 is increased. Since the output impedance of the try state 10 is sufficiently low, a transient phenomenon based upon electrostatic capacity existing in the bus 5 is not generated and the output B of a receiver 7 in a memory 4 is immediately turned from '1' to '0'.

Description

[Detailed Description of the Invention] [Summary] A transient phenomenon occurs due to the capacitance existing in a bus to which multiple bus masters are connected, and a change in the logic level of the bus is caused by a change in the output impedance of the bus master. Prevent delays.

[Industrial application field]

The present invention relates to a device in which a plurality of bus masters are connected to one bus by wired OR (or function is realized isometrically by directly connecting the outputs of logic elements), and in particular, This invention relates to a bus control method that prevents delays in operating time due to capacitance.

In devices where a single bus has multiple bus masters representing exclusive rights to the bus, such as computers in which multiple processors use a common bus to access memory, it is important to save logic elements and improve logic efficiency. There is a connection method called wire FOR, which is effective for speeding up and reducing power consumption, in which the lotus mask of each processor is connected to a lotus.

In this case, in order to increase the speed of the device, it is necessary that when one bus master relinquishes the right to occupy the bus, another bus master can immediately hold the right to occupy the bus.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a conventional bus master connection, and FIG. 4 is a diagram explaining the operation of FIG. 3.

For example, bus masters 2 and 3 of processors are connected to the bus 5, and a memory 4 is connected as a load. Control signals from bus masters 2 and 3 are wired ORed on bus 5. The signal in this case is negative logic,
When both bus masters 2 and 3 are not sending signals to the bus 5, the voltage of the power supply Vc is applied by the pull amplifier resistor 1, and the logic on the bus 5 is "1".

Since bus masters 2 and 3 are the same, the operation of bus master 2 will be explained using FIG. The tri-state 6 of the Hasmaster 2 lowers its output impedance and absorbs current from the bus when the enable signal applied from the terminal A is "1" as shown in Figure 4 (■), so the logic of the bus 5 is 0''.

Here, when the bus master 2 completes using the bus 5, the enable signal given from the terminal A changes from "l" to "0".
Changes to Tri-state 6 has an enable signal “l”
” to “0”, the output impedance becomes high as shown in FIG. 4, indicating that the bus master 2's right to occupy the bus has ended.

As the impedance of the tristate 6 becomes higher, there is no driver on the bus 5 that absorbs the current, and the potential rises due to the current supplied by the pull-up resistor 1, and its logic becomes "1". .

However, since the capacitance exists on the bus 5 as described above, a transient phenomenon occurs as shown in FIG. 4, and the potential of the bus 5 gradually increases. Therefore, the timing at which the output B of the receiver 7 of the memory 4, which is the km of the bus 5, changes from "1" to "0" is delayed by a time T, as shown in FIG. 4, until the input reaches the dark value. That will happen.

[Problem that the invention seeks to solve]

As mentioned above, conventionally, the terminal A of the bus master shown in Figure 4 ■
A time difference T occurs from the time point at which the enable signal applied from 1 to 2 changes to the time point at which the receiver output B of the memory changes as shown in FIG. Because of this time difference T, there is a problem in that it is necessary to always have time margin in the bus design, which is a big problem in increasing the speed.

In view of these problems, the present invention changes the logic of the lotus 5 while the bus master does not have the right to occupy the bus, that is, while the tri-state 6 of all the bus masters is in high impedance.
A gate fixed to I'' is provided to prevent the occurrence of a transient phenomenon and eliminate the time difference T.

[Means for solving problems]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

2 to 7 are the same as in FIG. 8 is a determination circuit that determines the logic of bus 5; 9 is a NOR circuit that performs a NOR of the enable signals of all bus masters; and 10 is a NOR circuit that determines the output of NOR circuit 9, so that bus masters 2 to N all occupy bus 5. When not in use, it is a tri-state that lowers the output impedance and raises the potential of the bus 5.

N indicates the Nth bus master.

The tristate 10 receives the NOR output of the enable signals of bus masters 2 to N from the NOR circuit 9, and
・When ~N tristate 6 has high impedance, the output impedance is lowered and the potential of bus 5 is increased, and when tristate 6 becomes low impedance and absorbs the current of bus 5, its output is The configuration has high impedance.

[Effect]

With the above configuration, the determining circuit 8 lowers the output impedance of the tristate 10 to
It is possible to easily supply current to the bus 5, eliminate the influence of the capacitance existing on the bus 5, and immediately change the logic level of the bus 5 in response to a change in the enable signal of the bus master.

〔Example〕

FIG. 2 is a diagram explaining the operation of FIG. 1.

In FIG. 1, bus masters 2, 3 . An enable signal is sent to the NOR circuit 9 of the determining circuit 8 from a terminal A that provides an enable signal to each tristate 6 of -.

For example, bus master 2 was using bus 5, but when this use is completed, the enable signal is changed to “
When the signal is changed from "1" to "0" and sent from terminal A, the output impedance of the tristate 6 becomes high as shown in FIG.

At this time, since the enable signals of the bus masters 3 to N are all "0", the output of the NOR circuit 9 of the determining circuit 8 is the second
As shown in Figure 2, the output impedance of the tristate 10 changes from "0" to 1, as shown in Figure 2. and raises the potential of bus 5.

The output impedance of tristate 10 at this time is
Since the pull-up resistor 1 shown in FIG. 3 is negligibly low, no transient phenomenon based on the capacitance existing in the bus 5 occurs, and the output B of the receiver 7 of the memory 4 is As shown in (2), it immediately changes from "1" to "0".

〔Effect of the invention〕

As explained above, the present invention enables high-speed operation because when one bus master relinquishes bus occupancy, there is no delay time caused by transient phenomena on the bus for another bus master to secure bus occupancy. It can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 2 is a diagram explaining the operation of FIG. 1, FIG. 3 is a block diagram showing an example of conventional bus master connection, and FIG. FIG. 4 is a diagram illustrating the operation of FIG. 3; In the figure, 1 is a pull-up resistor, 2.3 is a bus master, 4 is a memory, 5 is a bus, 6.10 is a tristate, 7 is a receiver, 8 is a deterministic circuit, and 9 is a NOR circuit.・,) Figure 1 Figure 1 movement 4γU the other day - 9 n 2nd flash

Claims (1)

[Claims] In a device in which there are a plurality of bus masters connected to one bus (5) by wired OR, there is provided a NOR circuit (9) that inputs all tri-state (6) enable signals of the bus masters; , a confirmation tristate (10) using the output of the NOR circuit (9) as an enable signal is provided, the confirmation tristate (10) is connected to the bus (5), and the bus master's tristate (6) is connected to the confirmation tristate (10). ) becomes “1”, the confirmation tristate (
The output impedance of 10) is set to high impedance,
When the enable signals of the tri-state (6) of the bus master all become “0”, the confirmation tri-state (1
A bus control method characterized by lowering the output impedance of the bus (5) and increasing the potential of the bus (5).