JPS62131337A - Response signal generation circuit - Google Patents

Abstract

PURPOSE:To improve a throughput even in a system including a device slow in accessing by providing a control register and a counter which can select whether a response signal is made generate immediately or with a delay. CONSTITUTION:Normally, an ACK61 is '1'. When the response signal is generated to a fast access device, the output Q of a control register 10 is set to '1'. An input signal CS21 is '0' while accessing. Therefore, the output of a gate 20 is '0', and the output of a gate 30 goes to '1', then an accessing is generated, and at the moment of an input signal CSDMA41 changes from '0' to '1', the ACK61 is made '0'. For a device with the slow accessing, '0' is written on the output Q of the control register 10, and a counter 90 is operated from the time of an input A1 and the CSDMA go to '1', and the change of the response signal ACK61 to '0' is delayed for a regulated time.

Description

[Detailed Description of the Invention] [Summary] When accessing the internal registers of an LSI, the response signal generation time can be adjusted using a counter depending on the register selection when accessing a fast access register or a slow access register. By controlling the response time of the response signal generation circuit, the throughput of the system is increased.

[Industrial application field]

The present invention relates to improvements in response signal generation circuits.

In order to process instructions in an appropriate time, it is desirable that the internal registers of the LSI be configured to be able to control the generation time of a response signal according to the access speed.

[Conventional technology]

Conventionally, the generation of a response signal to a register access is
If there are registers that are accessed slowly, the response speed is set according to the slowest accessed register among them, so that instruction processing can be performed in all registers at an appropriate time.

[Problem that the invention seeks to solve]

According to the above-mentioned conventional system, the high-speed access registers have unnecessary wasted time, and the input processing ability of the system as a whole is hindered by the slow-access registers, resulting in a decrease in the amount of output. That is, there is a drawback that the throughput is reduced.

[Means for solving problems]

According to the present invention, as shown in FIG. 1, a first circuit 1 includes a flip-flop circuit whose output level is fixed at a high or low level when specifying a pointer register, and a signal specifying a control register. a second circuit 2 consisting of a logic gate that outputs a high or low level signal depending on the output signal level given from the first circuit when given, and connected to the output section of the second circuit;
The problem is also solved by the response signal generation circuit of the present invention, which is comprised of a third circuit consisting of a logic gate circuit having a counter circuit that operates when a slow-access register designation signal is applied.

[Operation] According to the present invention, when writing register select data to a pointer register, for example, in order to access an internal register of an LSI, the first circuit stores the data in a flip-flop circuit, and stores the data in the selected internal register. A high or low level output is generated depending on whether the register is a fast access or slow access register, and this is applied to the second circuit. The second circuit provides a level signal to the third circuit when the internal register is accessed, depending on whether the data is stored in the first circuit, that is, fast access or slow access, and the third circuit is provided with a level signal at the same time. A response signal is output in conjunction with other access signals. At this time, the time until the response signal is generated is changed depending on whether or not a counter is connected.

〔Example〕

The present invention will be described in detail according to the illustrated embodiments.

FIG. 1 is a circuit diagram showing an embodiment of the response signal generating circuit of the present invention. In the figure, 10 is a D flip-flop circuit, 20 is a NOR gate, 30.40.50.60.7
0.80 is a NAND gate, and 90 is a counter circuit.

Writing of fast or slow access register selection data to flip-flop circuit 10 is performed as follows.

The clock input terminal CLK of °l" or °O-no 10 to be written to the input terminal 11 becomes low level, and the data of the input terminal 11 is written at the rise from the low level to the high level, and the data is output. An output signal of 1' or "0° level appears at terminal Q.

In a normal state where there is no access and there is no need for this response signal generation circuit to generate a response signal, the input signal REA of this circuit is
D 31 is low level “0”, input signal *CS 21 is high level “1°, input signal *RESt!T 14 is high level “1°, input signal [611 is °1° or °0]
”, the input signal P /D 12 is low level “0゛,
The input signal line ITE13 is low level “O′1 human input signal C
The SDM^41 is at a low level ``0'', the input signal ^191 is ``1'' or ``0'', and the CLK input 92 is given a clock signal.

In this case, the response output *XACK61 of this circuit is held at high level "1".

When an access occurs, the response signal generation circuit generates a response signal as follows.

At the time of access, if the input signal *C321 is written to a low level, this response signal generation circuit immediately outputs a response signal when there is an access.

The response signal is a response output at low level '0'* XACK
Output from 61.

That is, the gate 20 receives the output Q of the flip-flop circuit 10.
Since a high level "1" signal is input from the gate 30, its output becomes a low level "0".
The gate 40 outputs a high level "1" in response to a low level input from the gate 30 and the input signal C5DMA4.
The input of high level '1' from gate 50 gives a signal of low level '0' to gate 50.

The gate 50 inputs a signal of high level "1°" to the gate 60, and generates a response signal of low level "0'" at the output 61.

When the output Q of the flip-flop circuit 10 is written to low level "0", this response signal generation circuit generates a low level "0" response signal *XAC after access.
is not output immediately from 61.

At the time of access, the output of the gate 20 becomes high level ``1'', and when the input signal READ 31 is high level ``1'',
The output of gate 30 becomes low level "0", and gate 4
The output of 0 becomes a high level "l". C of counter 90
Since the ARY output 93 is at the low level "0°," the output of the gate 50 is at the low level "0°," and the response signal *XACK61 is not output at this time.

When the output of the gate 20 is at a high level 1, and the counter input *A191 and C5DMA 41 are at a high level 1, due to access, the counter 90 starts counting. When the counter reaches a full count, a high level °1' signal is generated at the output 93, the output of the gate 50 is set at high level '1', and a response signal *χACK is output from 61.

The signal at output 93 is also applied to gate 70, which causes clock signal CL to stop inputting clock signal 92 to the counter. Therefore, output 93 is C5DMA 41 and *A1
The signal continues to be output until 91 reaches the low level °O''.

There can be a delay depending on the frequency of the clock signal from when access is started until the response signal *XACX is sent.

〔Effect of the invention〕

The present invention provides a circuit that makes it possible to select between high-speed and low-speed response, and achieves an improvement in throughput even in a system that includes devices with slow access, and its effects are extremely significant.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the response signal generating circuit of the present invention. In the figure, 10 is a flip-flop circuit, 20 is a NOR gate, 30, 40, 50, 60, 70, 80 is a NAND gate, and 90 is a counter circuit. *: Negative logic diagram 1

Claims (1)

[Claims] A first circuit (1) equipped with a flip-flop circuit that fixes the output level to high or low level when specifying a pointer register, and a signal provided from the first circuit when a signal specifying a control register is provided. A second circuit (2) consisting of a logic gate that outputs a high or low level signal depending on the output signal level, and a signal specified by a slow-access register connected to the output section of the second circuit. and a third circuit (3) comprising a logic gate circuit having a counter circuit that operates at certain times.