JPS62187280A - Time synchronizing device - Google Patents

Time synchronizing device

Info

Publication number
JPS62187280A
JPS62187280A JP61030055A JP3005586A JPS62187280A JP S62187280 A JPS62187280 A JP S62187280A JP 61030055 A JP61030055 A JP 61030055A JP 3005586 A JP3005586 A JP 3005586A JP S62187280 A JPS62187280 A JP S62187280A
Authority
JP
Japan
Prior art keywords
time
circuit
time information
clock
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61030055A
Other languages
Japanese (ja)
Inventor
Takayuki Hishinuma
菱沼 孝之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61030055A priority Critical patent/JPS62187280A/en
Publication of JPS62187280A publication Critical patent/JPS62187280A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To synchronize automatically the time of plural information processors in automatic operation with one another by incorporating a timer circuit and supplying time information to other plural information processors. CONSTITUTION:Clock pulses sent by an oscillator 2 are frequency-divided by a frequency circuit 3 into a clock of frequency suitable to a timer circuit 5 and information processors 9 and 10. Those frequency-divided clock pulses are sent to the processors 9 and 10 through a clock pulse sending circuit 4. The processors 9 and 10 operate the internal timer circuit with the clock pulses 11. The circuit 5 operates with the clock pulses which are frequency-divided by the circuit 3 and its time information 12 is supplied to the processors 9 and 10 through a time information sending circuit 6. Even if the processor 10 stops operating temporarily and a difference in time from the time of the device 9 is generated, the time information 12 is received from the circuit 6 when operation is restarted and a timer circuit in the processor 10 becomes equal to time information 12, so that time synchronism is obtained between the processors 10 and 9.

Description

【発明の詳細な説明】 1産業上の利用分野〕 本発明は計時回路を内蔵する複数の情報処理装置間の時
刻情報を同期させる時刻同期化装置に関する。
DETAILED DESCRIPTION OF THE INVENTION 1. Field of Industrial Application The present invention relates to a time synchronization device that synchronizes time information between a plurality of information processing devices each having a built-in time measurement circuit.

〔従来の技術〕[Conventional technology]

従来の時刻同期化装置は、複数の情報処理装置に対して
、その装置の内蔵する計時回路に同期用のクロックパル
スだけを送出することによって時刻の同期化を行なって
いた。
Conventional time synchronization devices synchronize the times of a plurality of information processing devices by sending only synchronization clock pulses to the clock circuits built into the devices.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

したがって、この従来の時刻同期化装置は、情報処理装
置が運転中の時には有効である。しかし、情報処理装置
が夜間、又は休日等に運転を中止した場合には、その情
報処理装置が内蔵する計時回路は時刻同期化装置からの
クロックパルスを受信する回路が動作しなくなるため、
各自のクロックにより動作し、他装置との時刻の同期が
とれなくなる。この為、その情報処理装置が運転を再開
し時には、各情報処理装置内の計時回路の時刻情報に差
があることになり、人手により正確な時刻情報を入力し
、時刻を同期させる必要があり、非省力的であり、かつ
自動運転に適さないという問題点があった。
Therefore, this conventional time synchronization device is effective when the information processing device is in operation. However, if an information processing device stops operating at night or on a holiday, the timekeeping circuit built into the information processing device will no longer operate, and the circuit that receives clock pulses from the time synchronization device will no longer operate.
Each device operates using its own clock, making it impossible to synchronize the time with other devices. Therefore, when the information processing equipment resumes operation, there will be a difference in the time information of the clock circuits in each information processing equipment, and it is necessary to manually enter accurate time information and synchronize the times. However, there were problems in that it was not labor-saving and was not suitable for automatic driving.

本発明の目的は、計時回路を内蔵した自動運転の複数の
情報処理装置に、正確な時刻情報およびクロックパルス
を供給し、各情報処理装置の時刻を同期させることを可
能とする時刻同期化装置を提供することにある。
An object of the present invention is to provide a time synchronization device that supplies accurate time information and clock pulses to a plurality of autonomously operating information processing devices each having a built-in timekeeping circuit, thereby making it possible to synchronize the time of each information processing device. Our goal is to provide the following.

r問題点を解決するための手段] 本発明の装置は、基本周波数信号を発生する信号発生手
段と、前記信号発生手段から供給される基本周波数信号
を分周してクロックパルスを発生し時刻情報修正信号の
供給に応答してクロックパルスの位相を修正する分周手
段と、前記クロックパルスの供給をうけて外部装置に分
配する第1の分配手段と、前記クロックパルスの供給に
応答して計時し時刻情報を発生する計時手段と、前記時
同情報の供給をうけて前記外部装置に分配ずろ第2の分
配手段と、前記時刻情報と外部よりの時報信号との供給
に応答して前記時刻情報を修正する時刻情報修正信号を
発生ずる時刻修正手段とを謀んで構成される、 〔実施例1 本発明の実施例について図面を参照して説明する。
Means for Solving Problems] The apparatus of the present invention includes a signal generating means for generating a fundamental frequency signal, and a clock pulse is generated by dividing the fundamental frequency signal supplied from the signal generating means to generate time information. a frequency dividing means for correcting the phase of a clock pulse in response to the supply of a correction signal; a first distribution means for receiving the clock pulse and distributing it to an external device; and a timekeeping means in response to the supply of the clock pulse. a second distribution means for distributing time information to the external device in response to the supply of the time information; and a second distribution means for generating the time information in response to the supply of the time information and a time signal from the outside. Embodiment 1 An embodiment of the present invention will be described with reference to the drawings.

第1図は本発明による時刻装置の一実施例のブロック図
である。
FIG. 1 is a block diagram of an embodiment of a time device according to the present invention.

本実施例の時刻同期化装置1は、高精度の発振器2と、
その発振器より出力されたクロックパルスを分周する分
周回路3と、分周されたクロックパルスを池の装置へ送
出するクロックパルス送出回路4と、分周されたクロッ
クパルスによって時刻を刻む計時回路5と、計時回路5
の時刻情報を他の装置へ送出する時刻情報送出回路6と
、計時回路5の時刻情報と外部時計8からの時報信号1
3とを比較して、外部時計8の正確な時刻に同期させる
ために分周回路3へ修正を指示する時刻修正回路7とか
ら構成されている。
The time synchronization device 1 of this embodiment includes a high-precision oscillator 2,
A frequency dividing circuit 3 that divides the frequency of the clock pulse output from the oscillator, a clock pulse sending circuit 4 that sends the divided clock pulse to the Ike device, and a timekeeping circuit that keeps time using the divided clock pulse. 5 and clock circuit 5
a time information sending circuit 6 that sends out time information to other devices; time information from the time measurement circuit 5 and time signal 1 from an external clock 8;
3 and a time adjustment circuit 7 which instructs the frequency dividing circuit 3 to make corrections in order to synchronize with the accurate time of an external clock 8.

次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.

時刻同期化装置1には、複数の情報処理装置9゜10お
よび外部時計8が接続されている。発振器2より発せさ
れたクロックパルスは、分周回路3によって計時回路5
及び情報処理装置9,10に適する周波数のクロックに
分周される。この分周されたクロックパルスは、クロッ
クパルス送出回路4を経由して情報処理装置9および1
0に送られる。
A plurality of information processing devices 9 and 10 and an external clock 8 are connected to the time synchronization device 1 . The clock pulse emitted from the oscillator 2 is passed to the clock circuit 5 by the frequency divider circuit 3.
And the frequency is divided into a clock having a frequency suitable for the information processing devices 9 and 10. This frequency-divided clock pulse is transmitted to the information processing devices 9 and 1 via the clock pulse sending circuit 4.
Sent to 0.

情報処理装置9および10は、内蔵の計時回路をクロッ
クパルス11によって動作させる6分周回路3で分周さ
れたクロックパルスにより、計時回路5は動作し、その
時刻情報は時刻情報送出回路6を経由して、情報処理装
置9および10へ供給する、 ここでもし情報処理装置10が一時運転を中正すると、
クロックパルス1]を受けることが出来ないので情報処
理装置10の内部の計時回路は、その装置内のクロック
で動作する為に、情報処理装置9と時刻の同期がとれず
時刻に差が生ずる。
In the information processing devices 9 and 10, the clock circuit 5 is operated by the clock pulse frequency divided by the divide-by-6 circuit 3, which operates the built-in clock circuit by the clock pulse 11, and the time information is sent to the time information sending circuit 6. If the information processing device 10 temporarily suspends operation,
Since the clock pulse 1] cannot be received, the internal clock circuit of the information processing device 10 operates using the clock within the device, and the time cannot be synchronized with the information processing device 9, resulting in a time difference.

その後、情報処理装置10が運動を再開した時、時刻同
期化装置lより時刻情IJvI12を受けとり、情報処
理装置10に内蔵する計時回路の時刻は、時刻情報12
と等しくなる。情報処理装置つと計時回路5は、同一の
発振器2によって動作してい゛るので時刻は同期してい
る。
After that, when the information processing device 10 resumes exercise, it receives the time information IJvI 12 from the time synchronization device l, and the time of the clock circuit built in the information processing device 10 is determined by the time information 12.
is equal to Since the information processing device and the clock circuit 5 are operated by the same oscillator 2, their times are synchronized.

このようにして、情報処理装置10は、情報処理装置9
と時刻の同期をることか出来る。
In this way, the information processing device 10
You can synchronize the time with

また、外部時計8からの時報信号13と、計時回路5の
時刻情報を時刻修正回路7で比較および誤差の算出を行
ない、誤差を修正するように分周回路3ヘクロツクパル
スの早送り又は、遅送りの指示をする信号を出す。
In addition, the time signal 13 from the external clock 8 and the time information from the clock circuit 5 are compared in the time correction circuit 7 and an error is calculated, and the clock pulses of the frequency dividing circuit 3 are fast-forwarded or slow-forwarded so as to correct the error. Give a signal to give instructions.

し発明の効果〕 本発明には以上説明したように、時刻同期化装置に31
時回路を内蔵し、池の複数の情報処理装置l\時刻情・
服を供給することにより、自動運転下の複数の情報処理
装置の時刻を自動的に同期させることができるという効
果がある。
[Effects of the Invention] As explained above, the present invention has a time synchronization device equipped with 31
Built-in time circuit, Ike's multiple information processing devices
By supplying clothes, it is possible to automatically synchronize the times of multiple information processing devices under automatic operation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による時刻同期化装置の一実施例のブロ
ック図である。 1・・・時刻同期化装置、2・・・発振器、3・・・分
周回路、4・・・クロックパルス送出回路、5・・・計
時回路、6・・・時刻情報送出回路、7・・・時刻修正
回路、8・・・外部時計、9・・・情報処理装置、10
・・・情報処理装置、1】・・・クロ・ツクパルス、1
2・・・時刻情報、13・・・時報信号。 第 l 団
FIG. 1 is a block diagram of an embodiment of a time synchronization device according to the present invention. DESCRIPTION OF SYMBOLS 1... Time synchronization device, 2... Oscillator, 3... Frequency dividing circuit, 4... Clock pulse sending circuit, 5... Time measuring circuit, 6... Time information sending circuit, 7. ... Time adjustment circuit, 8... External clock, 9... Information processing device, 10
... Information processing device, 1] ... Kuro Tsuku Pulse, 1
2...Time information, 13...Time signal. Group I

Claims (1)

【特許請求の範囲】 基本周波数信号を発生する信号発生手段と、前記信号発
生手段から供給される基本周波数信号を分周してクロッ
クパルスを発生し時刻情報修正信号の供給に応答してク
ロックパルスの位相を修正する分周手段と、 前記クロックパルスの供給をうけて外部装置に分配する
第1の分配手段と、 前記クロックパルスの供給に応答して計時し時刻情報を
発生する計時手段と、 前記時刻情報の供給をうけて前記外部装置に分配する第
2の分配手段と、 前記時刻情報と外部よりの時報信号との供給に応答して
前記時刻情報を修正する時刻情報修正信号を発生する時
刻修正手段とを含むことを特徴とする時刻同期化装置。
[Scope of Claims] Signal generating means for generating a fundamental frequency signal; and a clock pulse is generated by frequency-dividing the fundamental frequency signal supplied from the signal generating means, and the clock pulse is generated in response to the supply of a time information correction signal. a first distribution means that receives the clock pulse and distributes it to an external device; a clock means that measures time and generates time information in response to the clock pulse supply; a second distributing means that receives the time information and distributes it to the external device; and generates a time information correction signal that corrects the time information in response to the time information and the external time signal signal. A time synchronization device comprising: time adjustment means.
JP61030055A 1986-02-13 1986-02-13 Time synchronizing device Pending JPS62187280A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61030055A JPS62187280A (en) 1986-02-13 1986-02-13 Time synchronizing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61030055A JPS62187280A (en) 1986-02-13 1986-02-13 Time synchronizing device

Publications (1)

Publication Number Publication Date
JPS62187280A true JPS62187280A (en) 1987-08-15

Family

ID=12293138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61030055A Pending JPS62187280A (en) 1986-02-13 1986-02-13 Time synchronizing device

Country Status (1)

Country Link
JP (1) JPS62187280A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03107790A (en) * 1989-09-21 1991-05-08 Toshiba Corp Remote monitor and control equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60108766A (en) * 1983-11-17 1985-06-14 Sumitomo Electric Ind Ltd Voltage drop measuring apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60108766A (en) * 1983-11-17 1985-06-14 Sumitomo Electric Ind Ltd Voltage drop measuring apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03107790A (en) * 1989-09-21 1991-05-08 Toshiba Corp Remote monitor and control equipment

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