GB1086664A - An offset control system for traffic signal - Google Patents

Abstract

1,086,664. Road traffic signals. TATEISI ELECTRONICS CO. July 25, 1966 [July 30, 1965], No. 33394/66. Heading G4Q. A master controller supplies clock pulses which can vary between 40 and 120 per second, split and offset selection signals, and a synchronizing pulse transmitted once per cycle, and the local controller is provided with means for counting the clock pulses and for altering the counting means to change the cycle length slowly when a new offset is required. The counting means comprises a scale of six counter (1C1, Fig. 1, not shown) feeding a further counter (1C2) feeding two decimal counters (2C1 and 2C2, Fig. 2, not shown). The final counter normally produces an output (on line 3) after every 4800 pulses and this output starts the green period. The decimal counters are connected to pinboards (210-213 and 220- 224) which can be set manually and two of which are selected by the split and offset signals from the master controller to give a required split signal (on terminal 4) which terminates the green period at a desired count and an offset signal (on terminal 202) which should coincide with the synchronizing signal. The synchronizing signal lasts for 144 clock pulses and is applied (over line 401, Fig. 3) to a flip-flop (3F1) to which the local offset signal is also applied' (over line 202). If the two signals coincide the flip-flop remains set and operation proceeds normally. If the synchronizing signal is late, due to a change in offset, and output from the flip-flop (on line 301) stops the decimal counters, and the output of the further counter (1C2) is passed to a fifth counter (3C1, via line 102). If this fifth counter fails to count ten before the synchronizing pulse arrives the system is now synchronized and normal operation is resumed. If it does complete its count, the decimal counters resume counting and an output from the first decimal counter passes to a sixth counter (4C1) which is used to determine whether the synchronizing pulse is delayed more or less than 50% of the cycle time; according to which answer is given the scale of the further counter (1C2) is altered from its normal eight to either seven or nine so that synchronization is achieved in the minimum number of cycles.