US3562704A - Offset control system for traffic signal - Google Patents

Abstract

THIS INVENTION RELATES TO AN OFFSET CONTROL SYSTEM FOR TRAFFIC SIGNALS. A SYSTEM IS DISCLOSED WHICH INCLUDES A SEPARATE CONTROLLER FOR EACH LOCAL SIGNALING DEVICE, WITH A MASTER CONTROLLER BEING COUPLED WITH EACH LOCAL CONTROLLER AND OPERATIVE TO PROVIDE SYNCHRONIZING SIGNALS THERETO. THE SYSTEM USES PULSE GENERATING AND COUNTING CIRCUITS TO ACCOMPLISH SELECTED ADJUSTMENTS FOR THE OFFSET OF INDIVIDUAL CONTROLLERS. CIRCUIT DETAILS FOR A PREFERRED EMBODIMENT OF THE INVENTION ARE PROVIDED.

Description

Feb. 9, 1971- SHUNSUKE IWAMOTO E'I'AL 3,562,704

OFFSET CONTROL SYSTEM FOR TRAFFIC SIGNAL Original Filed Aug. 1. 1986 2 Sheets-Sheet 2 FIG. 3.

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United States Patent 01 3,562,704 Patented Feb. 9, 1971 3,562,704 OFFSET CONTROL SYSTEM FOR TRAFFIC SIGNAL Shunsuke Iwarnoto, Hiroo Watanabe, and Tadao Endo, Kyoto, Japan, assignors to Omron Tateisi Electronics Co., Kyoto, Japan, a corporation of Japan Continuation of application Ser. No. 569,495, Aug. 1, 1966. This application Sept. 17, 1969, Ser. No. 859,481 Claims priority, application Japan, July 30, 1965, 40/ 46,489 Int. Cl. G08g N US. Cl. 34040 11 Claims ABSTRACT OF THE DISCLOSURE This invention relates to an offset control system for traffic signals. A system is disclosed which includes a separate controller for each local signaling device, with a master controller being coupled with each local controller and operative to provide synchronizing signals thereto. The system uses pulse generating and counting circuits to accomplish selected adjustments for the offset of individual controllers. Circuit details for a preferred embodiment of the invention are provided.

This application is a continuation of US. application Ser. No. 569,495, filed Aug. 1, 1966, bearing the same title as this application, and now abandoned.

In order to enable a smooth trafiic flow along a road provided with many local traffic signal controllers it is necessary to control them systematically from a master controller. Offset control is one of the most important problems involved in such a control system. Offset control is performed in different ways. Local controllers are generally designed to be capable of different offsets, one of which is selected most suitable for the present trafiic condition. When the condition varies, however, it is necessary to change from the offset that has been followed to another offset most suitable for that varied condition. Such offset change is usually remotely controlled from the central controller. When the offset has been changed, an abrupt change of the signal indication in accordance with the new offset would certainly cause disturbance to traffic. Therefore, it is required to gradually change from the old to the new offset, and that in as short a period of time as possible.

Most prior art offset control systems employ mechanical moving parts, contact switches, etc., which pose vari ous problems in maintenance, reliability and service life.

Accordingly, it is one object of the invention to provide an offset control system which employs static, logic components eliminating all mechanical contacts, relays, electron tubes, etc.

Another object of the invention is to provide an offset control system as aforesaid which makes it possible to change from one to another offset in such a manner as to cause as little disturbance to traffic as possible.

Another object of the invention is to provide an offset control system as aforesaid which makes it possible to complete such an offset change in a relatively short period of time.

In accordance with the invention, each local signaling device is provided with a controller. They are centrally controlled from a remote master controller. The master controller gives the local controllers synchronizing signals in the same cycle as the signal cycle length. The signal cycle length is the time period between one green signal indication and the next green signal indication.

In each local controller, the green signal is indicated a predetermined period of time after a synchronizing signal has been received from the master controller. This time period is commonly referred to as offset. A plurality of offsets are available, and selection among them is effected by an offset selection signal received from the master controller. When the local controller is normally operating in accordance with a selected offset, the offset signals are produced in the same cycle as the synchronizing signals. The green signal is illuminated a predetermined period of time after each offset signal has been produced. However, when an offset selection signal has been given to change from the present offset to a different one, the first offset signal produced thereafter will not coincide with the synchronizing signal. If the offset signal happens to be produced a predetermined period of time, for example, less than 10 percent earlier than the synchronizing signal, the signal cycle length is elongated, thereby causing both signals to coincide. The percentages here and in the following pages are given against the normal signal cycle length of If the offset signal happens to be produced more than 10% earlier than the synchronizing signal, the signal cycle length is either elongated or shortened, thereby causing both signals to coincide and reducing the period of time required for completion of the offset change.

The synchronizing signals are applied from the master controller to each local controller in the form of pulses. In addition, clock pulses are applied from the master controller to the local controllers. The number of clock pulses is within the range of 40 to per second. A predetermined number of clock pulses are counted to produce an offset signal in the form of a pulse. To this end, pulse counters are provided. The system of the invention is composed of static elements such as AND, NOT, OR, INHIBIT, or flip-flop elements.

The invention, with its above stated and other objects, features and advantages, will be better understood from the following detailed description of one embodiment thereof, with reference to the accompanying drawings, wherein:

FIGS. 1 to 4 are schematic blocl diagrams constituting the system of the invention.

Referring now in detail to the drawings, there is shown in FIG. 1 a terminal 1 to which cycle signals are applied from a master controller (not shown) which also supplies signals to terminals 5, 10, 20, 30, 40, 11, 12, 13 and 14 of the local controller. The cycle signal may comprise clock pulses, 40 to 120 in number per second. The signal cycle length can be varied by varying the number of the clock pulses given per second. Pulse counters 1C1 and 1C2 constitute a first group; and pulse counters 2C1 and 2C2 constitute a second group. The pulse counters 1C1 and 1C2 are hexanary and nonary counters, respectively; while the counters 2C1 and 2C2 are both decimal. The counter 1C2, however, normally operates as an octal counter, as will be explained later. In this case, when 4800 pulses have been applied to the terminal 1, one pulse appears at a terminal 3 in FIG. 2. This pulse is utilized to initiate the green signal indication.

In FIG. 2, a suitable source (not shown) applies an operating voltage through a terminal 2 to a pair of AND circuits generally designated by 6 and 7, respectively. The circuit 6 comprises four pinboards 210, 211, 212 and 213 of the same construction, with four terminals 10, 20, 30 and 40. Each pinboard is provided with ten holes 230 connected to the ten output lines of the counter 2C1 and ten holes 230' connected to the ten output lines of the counter 2C2. A split selection signal is applied from the master controller to a selected one of the four terminals 10 to 40. The arrangement is such that the split, that is, the percentage of the time period of the green signal indication to one signal cycle, is determined by which of the four terminals receives the split selection signal. With a pin inserted into a selected one of the holes 230 and another pin in a selected one of the holes 230', an output appears at a terminal 4, and this output is utilized to terminate the green signal indication that was initiated by the signal at the terminal 3.

In the illustrated embodiment, four different splits are available as there are four pinboards. It will be seen that which of the four different splits is selected is determined by which of the four terminals 10 to 40 receives a selection signal. For example, if the selection signal has been applied to the terminal 10, the split as determined by the pinboard 210 has been selected. Each of the four splits as determined by the four pinboards can be varied by inserting the pins into different holes.

The other AND circuit 7 also comprises four pinboards 220, 221, 222 and 223 with four terminals 11, 12, 13 and 14, to which an offset selection signal is applied from the master controller. The four pinboards are of the same construction as the previously mentioned pinboards, and provide four different kinds of offsets, which are determined and can be varied in a manner similar to that in which the four splits are determined and varied.

Referring to FIG. 4, a terminal of the local controller receives synchronizing signals from the master controller, one for every 4800 pulses applied to the terminal 1. The synchronizing signals are off-pulses whose pulse width is 3% of the signal cycle length. Since the signal cycle length corresponds to 4800 clock pulses, the pulse width of the synchronizing signal corresponds to 144 clock pulses. The synchronizing signals are applied in the same cycle as the signal cycle.

Under the normal condition, that is, one of the four offsets has been selected and the system is operating accordingly, when a synchronizing signal is applied to the terminal 5, an offset signal is appearing on a line 202 at the same time. Then a flip-flop element 3P1 in FIG. 3 receives the offset signal at its 0 section and the synchronizing signal at its 1 section through a NOT element 4N3 in FIG. 4 and a line 401. Since the synchronizing signal has a greater pulse width than the offset signal, the flip-flop has its 1 section turned on to produce an output on a line 311. This output is applied through an OR element 3R1 to a NOT element 3N1, which produces no output on a line 301 connected to one of the two inputs of an OR element 1R3 (FIG. 1). The other input of the OR element 1R3, however, receives carry output pulses from the counter 1C2 through a line 111 in the following manner.

The synchronizing signal on the line 401 is also applied to a NOT element 3N2, which produces no output on a line 319 connected to one of the two inputs of an OR element 3R3. The offset signal on the line 202 is also applied to the 0 section of a flip-flop 3P2 so as to turn off its 1 section, so that no output is produced on a line 321 connected to the other input of the OR element 3R3. As a result, a NOT element 3N3 receives no input and consequently produces an output on a line 317 and its branch lines 304 and 307. The output on these lines turn on the 1 sections of flip-flops 4P2 and 4F3, respectively,

which produce an output on the lines 403 and 405, respectively, but no output on the lines 402 and 404 of their 0 sections.

The lines 403 and 405 are connected to the inhibit terminals of INHIBIT elements 1H2 and 1H4, respectively, while the lines 402 and 404 are connected through an OR element 1R1 to the inhibit terminal of an INHIBIT element 1H3. Consequently, the elements 1H2 and 1H4 produces no output, but the element 1H3 produces an output when the counter 1C2 has counted eight pulses from the hexal counter 1C1. The output of the element 1H3 is applied through an OR element 1R2 and an INHIBIT element 1H1 back to the counter 1C2 to reset it. Thus, the counter 1C2 now operates as an octal counter, producing one carry pulse for every 48 clock pulses at the terminal 1 and, due to the two decimal counters 2C1 and 2C2, one pulse appears at the terminal 3 for every 4800 pulses applied to the terminal 1. This means that under the nor- 4 mal condition, each signal cycle corresponds to the period of time during which 4800 clock pulses are applied to the terminal 1.

When it is required to change from the offset presently followed to a different offset, the master controller applies an offset selection signal to a different one of the terminals 11 to 15, as previously mentioned. When a new offset has thus been selected, the signal cycle length is gradually and temporarily lengthened or shortened so that the offset signal and the synchronizing signal finally coincide, thereby restoring the original normal signal cycle length and providing traffic signal indications based on the newly selected offset. In this case, the temporary lengthening or shortening of the signal cycle length is kept within 12.5% so as to enable a step-by-step transfer from the old to the new offset, because a greater percentage would certainly disturb traffic.

If, under the new offset, the first offset signal happens to be produced less than 10% earlier than the first synchronizing signal, the signal cycle length is lengthened (Case I). If the offset signal happens to be produced more than 10% (inclusive) earlier than the synchronizing signal (Case II), the signal cycle length is either shortened (Case Ila) or lengthened (Case 111)).

In Case I, when the first offset signal is applied through the line 202 to the 0 section of the flip-flop 3P1, an output is produced on a line 302 and the output on the line 311 disappears, so that the NOT element 3N1 produces an output to be applied through the OR element 1R3 to the counter 2C1 to stop it. The output on the line 301 is maintained until the late coming synchronizing signal is applied to the 1 section of the flip-flop 3P1 to turn it on, thereby causing the output on the line 301 to disappear and, consequently, until that time the counters 2C1 and 2C2 are stopped. This means that the signal cycle length is lengthened. While the counters 2C1 and 2C2 are thus being stopped, a decimal counter 3C1, however, receives the output pulses from the counter 1C2 through a line 102, one pulse for every 48 pulses applied to the terminal 1, which corresponds to 1% of the signal cycle length of 4800 pulses. However, before 10 pulses (corresponding to 4800 pulses at the terminal 1 and 10% of the cycle length) have been counted by the counter 3C1, the late coming synchronizing signal comes into the 1 section of the flip-flop 3P1 (in Case I, the synchronizing signal is supposed to come in within 10% of the cycle length later than the offset signal), thereby causing the 1 section of the flip-flop 3F 1 to produce an output on the lines 311, 312 and 313 to reset the counter 3C1, so that no output is produced on its single output line 314. When the synchronizing signal has come in, the output on the line 301 disappears, so that the counter 2C1 resumes its counting operation. Thus, the counter 2C1 stops its operation with the offset signal, but resumes it with the synchronizing signal, so that in the next cycle, both signals coincide.

In Case II, the counter 3C1 will have counted ten pulses from the counter 1C2 before the synchronizing signal comes in, so that an output is produced on the line 314 to be applied to the 0 section of a flip-flop 3P3. As a result, an output appears on a line 315 and is applied through the OR element 3R1 to the NOT element 3N1, the existing output of which then disappears. This causes the counter 2C1 to resume its counting operation.

The output on the line 314 is also applied to the 1 section of a flip-flop 3P2 to turn the section on, so that an output is produced on a line 318. This output resets the counter 3C1 through the OR element 3R2 and the line 313 on one hand and is applied through a line 321 and the OR element 3R3 to the NOT element 3N3 on the other hand. Then, this NOT element produces no output on the lines 304, 307 and 316. Since the flip-flop 3P3 receives no input at its 1 section, no output is on the line 305, but the resetting output on the line 313 also appears on the line 306. Consequently, no output is produced on the lines 402 and 404, while an output exists on the lines 403 and 405, because the flip-flops 4P2 and 4P3 remain as they are. Then, the INHIBIT element 1H2 and 1H4 produces no output but the INHIBIT element 1H3 allows the output produced by the counter 1C2 having counted eight pulses to reset the counter 102. This means that the counter 1C2 operates as an octal counter, producing one pulse on the line 111 for every eight input pulses thereto corresponding to 48 clock pulses at the terminal 1.

The net result is that when the first offset signal under the new offset comes in through the line 202, the counter 1C2 continues its operation as an octal counter, while the counter 2C1 is stopped for 10% of the signal cycle length, thereby elongating the signal cycle length by 10% (or reducing by 10% the interval between the offset signal and the synchronizing signal), and then the first synchronizing signal comes in through the line 401.

This signal turns on the 1 section of the flip-flop 3P1, so that the output from its section disappears on the line 302. The signal on the line 401 is also applied to the NOT element 3N2, the output of which then disappears so that no output appears on the line 303. During the transient period of offset change, the 1 section of the flip-flop 3P3 is maintained in the off condition, so that no output is on the line 305. Then the NOT element 4N1 produces an output, which turns off the 1 section of a flip-flop 4F 1, whereupon the inhibition on the INHIBIT element 4H1 is removed, so that the output pulses from the counter 2C1 are applied to a counter 401. This counter is a quinary counter and produces on a line 412 one pulse for every five pulses it receives through a line 201 from the counter 2C1, corresponding to 2400 pulses applied to the terminal 1. Resetting of the counter 4C1 is effected by the synchronizing signal applied through a NOT element 4N3 and a line 411 to the counter.

When the next offset signal comes in through the line 202, the flip-flop 3P1 is reversed to produce an output on the line 302. This turns on the 1 section of the flip flop 4P1 to produce an output to be applied to the inhibit terminal of the INHIBIT element 4H1, which prevents the pulses on the line 201 from coming into the counter 4C1. In this case, if the olfset signal comes in less than 50% later than the previous synchronizing signal, the counter 4C1 produces no output on the line 412. However, if it comes in more than 50% later than the synchronizing signal, the counter produces an output on the line 412. In the former case (Case IIa), the signal cycle length is shortened and in the latter case (Case 111)), the cycle length is lengthened, so that the offset change can be completed in a shorter time than otherwise.

In Case Ila, when the offset signal comes in through the line 202, the counter 4C1 is stopped before it pro duces an output on the line 412, as mentioned just above. The offset signal on the line 202 is also applied through the line 320 to the flip-flop 3P2 to turn its 1 section off, so that the output on the lines 318, 313 and 306 disappear. At this time, no output exists on the lines 304, 305 and 307, as previously mentioned. As a result, the OR element 4R2 produces no output to be applied to the NOT element 4N2, the output of which then turns the 0 section of the flip-flop 4P3 on, so that an output appears on the line 404, but no output is on the line 405. On the other hand, no output is on the line 402, but an output is on the line 403. The net result is that the INHIBIT elements 1H2 and 1H3 prevents the corresponding outputs of the counter 102, and the inhibit element 1H4 only permits the corresponding output of the counter to be fed back thereto to reset the counter. This means that the counter 1C2 now operates as a heptal counter, producing one pulse on the line 111 for every seven carry pulses from the counter 1C1 (42 pulses at the terminal 1). Consequently, a signal appears at the terminal 3 when 4200 pulses have been applied to the terminal 1. This means that the signal cycle length is shortened by 12.5% of the normal cycle length of 4800 pulses.

Under the condition, within five signal cycles from the first offset signal under the new offset, the oifset signal overtakes the synchronizing signal and appears on the line 202 less than 9.5% earlier than the synchronizing signal, since the pulse width of the latter signal is 3%. When this offset signal is applied to the 0 section of the flip-flop 3P2, its 1 section is turned off and the counter 3C1 has its reset signal removed. However, before the counter 3C1 has counted 10 pulses from the counter 1C2 to produce an output on the line 314, the next synchronizing signal comes in through the line 401 to the 1 section of the flip-flop 3P1, whose output is applied through the line 312, the OR element 3R2 and the line 313 to the counter to reset it, so that the flip-flop 3P2 is kept as it is. The synchronizing signal on the line 401 also removes the output of the NOT element 3N2 on the line 319, so that with no signal on the line 321 at this time, the NOT element 3N3 produces an output on the lines 317 and 316. This reverses the flip-flop 3P3, thereby removing the output on the line 315 and producing an output on the line 305. The output on the line 317 is applied through the lines 304 and 307 to the 1 sections of the flip-flops 4P2 and 4P3, respectively, the outputs of which are applied to the inhibit terminals of the INHIBIT elements 1H2 and 1H4. Since the INHIBIT element 1H3 receives no inhibit signal, the counter 1C2 operates as an octal counter. In the next cycle, when an offset signal comes in through the line 202, the counter 2C1 is stopped temporarily until a synchronizing signal comes in through the line 401 less than 9.5% later, whereupon the counter 2C1 resumes its counting operation. Thus, in the next cycle both signals coincide, and the transfer from the old to the new offset has thus been completed.

In Case IIb where the offset signal comes in more than 50% later than the synchronizing signal, the counter 401 will have counted five pulses from the counter 2C1 before the inhibit signal (the offset signal) is applied to the IN- HIBIT element 4H1. The output of the counter 4C1 appearing on the line 412 is applied to the 0 section of the fiip-fiop 4P2 to turn the section on, so that an output is produced on the line 402, but no output on the line 403. On the other hand, since the flip-flop 4F3 has its 0 section off, no output is on the line 404 but an output is on the line 405. As a result, the INHIBIT elements 1H3 and 1H4 obstruct the corresponding outputs from the counter 1C2, but the INHIBIT element 1H2 allows the corresponding output of the counter to be applied back thereto to reset the counter. This means that the counter 1C2 now operates as a nonary counter, producing one pulse on the line 111 for every 54 pulses applied to the terminal 1. Consequently, a signal appears at the terminal 3 every time 5400 pulses have been applied to the terminal 1. In other words, the signal cycle length has been elongated by 12.5 of the normal cycle length of 4800 pulses. Under the condition, within 4 cycles of this elongated length, the offset signal comes to appear more than 90.5% later than the previous synchronizing signal, that is, precede the succeeding synchronizing signal by less than 9.5 This offset signal turns on the 0 sections of the flip-flops 3F1 and 3P2, so that the counter 3C1 produces no output on the line 314, thereby keeping the flipfiop 3P2 as it is. Then, the next synchronizing signal comes in less than 9.5 later, as mentioned just above, whereupon the output from the NOT element 3N2 disappears and, with no output on the line 321, the NOT element 3N3 produces an output on the line 317. This output is applied through the line 316 to the flip-flop 3P3 to turn its 0 section off, thereby removing the output on the line 315. On the other hand, the output on the line 317 is also applied through the lines 304 and 307 to the flip-flops 4P2 and 4P3 to turn their respective 1 sections on, so that an output appears on the lines 403 and 405, with no output on the lines 403 and 405. This means that the counter 1C2 now operates as an octal counter. With no output on the line 314, when an offset signal 7 comes in, in the next cycle, the counter 2C1 is temporarily stopped until a synchronizing signal comes in less than 9.5% later, whereupon the counter 2C1 resumes its counting operation in the manner previously mentioned. Thus, in the next cycle both signals coincide and the transfer from the old to the new offset has been completed.

In the above description specific pulse width, cycle lengths, and other operating parameters have been given. These details are only given as an aid in teaching the invention, but of course other parameters could be used. For example, if the pulse width of the synchronizing signal and the rate of the signal cycle length that is temporarily changed during the course of offset change are of the same percentage to the normal signal cycle length, that is, if the pulse width is instead of 3% and the rate of cycle change is also 5% instead of 12.5%, the system of the invention can operate without the circuit means for temporarily stopping the counters 2C1 and 2C2 when the offset signal approaches the synchronizing signal within 9.5%, until the latter signal comes in.

What we claim is:

1. An offset control system for use in a local traffic signaling device, comprising, in combination With a master controller adapted to provide clock pulses, synchronizing signals and an offset selection signal to be applied to said system: first counting means for counting a first predetermined number of said clock pulses to produce a carry pulse, said first predetermined number being selectively variable; second counting means provided with a plurality of output terminals and adapted to count said carry pulses from said first counting means to produce an output at the corresponding one of said terminals to the number of said carry pulses that have been counted; offset selecting circuit means connected to said output terminals of said second counting means and adapted to provide different offsets, one of which is selected upon combination of said offset selection signal and said output from said second counting means, and produce offset signals in accordance with said selected offset; first detecting circuit means for detecting an offset signal which does not coincide with a synchronizing signal; second detecting circuit means for detecting whether a succeeding offset signal comes in within a second predetermined number of said clock pulses after the preceding synchronizing signal was received; third circuit means for reducing said first predetermined number of clock pulses to be counted by said first counting means when said second detecting circuit means has detected that said offset signal has come in within said second predetermined number of clock pulses, and increasing said first predetermined number of clock pulses to be counted by said first counting means when said second detecting circuit means has detected that said offset signal has not come in within said second predetermined number of clock pulses.

2. The system as defined in claim 1, further including fourth circuit means for temporarily stopping the counting operation of said second pulse counting means when said first detecting circuit means has detected an offset signal not coinciding with a synchronizing signal.

3. The system as defined in claim 1, wherein said first detecting circuit means includes a flip-flop adapted to be set by an offset signal and reset by a synchronizing signal.

4. The system as defined in claim 2, wherein said fourth circuit means comprises fifth circuit means for producing a signal to stop the operation of said second pulse counting means when. said first detecting circuit means has de tected that an offset signal does not coincide with a synchronizing signal, and third counting means for counting a third predetermined number of said carry pulses from said first counting means to produce an output to be applied to said fifth circuit means so that said stop signal is removed.

5. The system as defined in claim 1, wherein said second counting means comprises a first decimal counter and a second decimal counter for counting said carry pulses from said first decimal counter, and wherein said second detecting circuit means comprises fourth counting means for counting said carry pulses from said first decimal counter and means responsive to said first detecting circuit means and said synchronizing signal for applying said carry pulses to said fourth counting means and preventing said carry pulses from being applied thereto when an offset signal has been applied to said means.

6. A traffic signal control system comprising:

(a) a master controller which provides synchronizing signals establishing a cycle for all the traffic signals associated with the system,

(b) a local controller including (i) a source of clock pulses,

(ii) pulse counting means stepped by said source of clock pulses and providing an output signal after a predetermined count thereof is reached, said output signal defining a cycle for the traffic signals associated with the local controller,

(iii) means providing an offset signal denoting a desired offset and a split signal denoting a desired split from said output signal, and

(iv) means operative when one of said synchronizing signals does not coincide with said offset signal to bring said signals into coincidence by I varying the signal cycle of the local controller.

7. A trafiic signal control system as recited in claim 6, wherein said control means further includes means varying the predetermined count of said pulse counting means when said signals do not coincide.

8. A traffic signal control system as recited in claim 6, wherein said signals are brought into coincidence by either elongating or shortening said signal cycle.

9. A traffic signal control system comprising:

(a) a master controller providing synchronizing signals,

(b) a pulse counting circuit adapted to make one forward step upon application thereto of a number of pulses corresponding to 1 percent of the length of a selected signal cycle, and providing an output signal when it has counted the number of pulses corresponding to percent of the length of the selected signal cycle,

(c) an offset setting circuit connected to said pulse counting circuit and providing an offset signal in response to the output signal therefrom,

(d) circuit means for detecting the degree to which the output signal from the offset setting circuit does not coincide with the synchronizing signal from the master controller, and

(e) means for changing the length of said forward step of said pulse counting circuit from 1 percent to a number greater or less than 1 percent, depending upon the degree detected by said circuit means.

10. A traffic signal control system comprising:

(a) a master controller providing synchronizing signals,

(b) a pulse counting circuit adapted to be stepped forward by clock pulses and producing output pulses on a plurality of output terminals thereof,

(c) a split setting circuit connected to the output terminals of said pulse counting circuit and producing from the output pulses thereon a split setting signal,

(d) an offset setting circuit also connected to the output terminals of said pulse counting circuit and producingi from the output pulses thereon an offset signal, an

(e) means receiving the synchronizing signal from said master controller and said offset signal and controlling said pulse counting means for establishment of a synchronous relation therebetween.

11. A traffic signal control system comprising:

(a) a master controller providing synchronizing pulses,

(b) a pulse counter adapted to make one forward step upon application thereto of a number of clock pulses corresponding to 1 percent of the length of a selected signal cycle and producing an output signal when it has counted the number of pulses corresponding to master controller and said offset signal to control 100 percent of the length of the selected signal cycle, said pulse counter for establishment of a synchronous (c) circuit means for producing a cycle initiating signal relation therebetween.

when said pulse counter has produced its output signal, References Cited (d) a split setting circuit producing from said output 5 UNITED STATES PATENTS a signal for terminating said cycle 1n1t1at1ng 3,252,133 5/1966 Auer et al- (e) an offset setting circuit connected to said pulse RALPH D, BLAKESLEE, Primary Examiner counter and producing an offset signal in response 10 to the production of said output signal therefrom, US. Cl. XR. and 34035, 41

(f) means receiving the synchronizing signal from said

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