US3754210A

US3754210A - Traffic light control systems

Info

Publication number: US3754210A
Application number: US00129482A
Authority: US
Inventors: J Preti
Original assignee: Societe de Fabrication dInstruments de Mesure SFIM SA
Current assignee: Societe de Fabrication dInstruments de Mesure SFIM SA
Priority date: 1971-03-30
Filing date: 1971-03-30
Publication date: 1973-08-21
Anticipated expiration: 1990-08-21

Abstract

A traffic light control system comprises two timers, one of which operates at a normal frequency and the other at a much higher frequency, the second timer controlling a programmer which acts on a logic circuit which controls a power circuit for the lights. A comparator compares the output signals of the timers, and indicates when the output signals of the two timers are identical or have a given shift, whereby any spurious signals do not affect the lights. The system can be designed to take into account an external command, the state of the traffic lights, and the traffic density. A plurality of such systems can be coordinated with a minimum of interconnections.

Description

United States Patent Preti 1 Aug. 21, 1973 TRAFFIC LIGHT CONTROL SYSTEMS Primary Examiner-William C. Cooper [75] Inventor: Jean Claude Preti, Clamart, France Parker & Hale [73] Assignee: Societe de Fabrication Dlnstruments de Mesure S.F.I.M., Garnier, [57] ABSTRACT France A traffic light control system comprises two timers, one I of which operates at a normal frequency and the other [22] 1971 at a much higher frequency, the second timer control- [211 App]. No.: 129,482 ling a programmer which acts on a logic circuit which controls a power circuit for the lights. A comparator compares the output signals of the timers, and indicates when the output signals of the two timers are identical or have a given Shift, whereby any Spurious signals do [58] Field of Search 340/41, 46, 40 not affect the fights- The system can be designed to [56} Reierences Cited take into account an external command, the state of the traffic lights, and the traffic density. A plurality of UNITED STATES PATENTS such systems can be coordinated with a minimum of in- 2,003,328 6/1935 Worrall 340/37 terconnections, 2,082,629 6/1937 Helmbright 340/46 UX 3,302,170 1/1967 Jensen et a1. 340/41 3,363,185 1/1968 Sanderson et a1. 340/40 X 12 Claims, 8 Drawing Figures 3,414,878 12/1968 Smith 340/41 3,537,067 10/1970 lshikawa 340/40 3 562,704 2/1971 lwamoto 340/40 I 600/1/ 75? 70 f /15 A0676 5Y5 751/ 7 F B00 (4) COU/VTR-Z L 1 7'5 j-pwamlmm 6 7 /02 f 060a5-8 o/ve $51 FOR 540% GROUP OF LIGHTS 7' BACKGROUND OF THE INVENTION This invention relates to systems for controlling the operation of a set of traffic lights, each of the groups of traffic lights in the set normally comprising three separate lights, namely green, amber and red.

The invention relates more particularly to systems of the type comprising a timer (hereinafter called a clock) which receives a control signal of given frequency and which delivers corresponding timing signals, a programmer which receives the timing signals and which delivers output signals representative of commands for switching the lights on and E, and a logic system which receives the output signals and which consequentially controls the operation of the power circuits for the lights.

SUMMARY OF THE INVENTION A first object of the invention is to provide an improved system of this type such that any spurious electric pulses induced into the system have no effect on the control of the traffic lights, thus rendering the operation of the system more reliable. Such spurious electric pulses often derive from the switching of electric circuits of motor cars, industrial lights and machines and electroluminescent flashlights.

A second object of the invention is to provide an improved system of this type such that in the operating cycle of the system there are intervals of time which can be lengthened or shortened to modify the control of the lights, for example to modify or clip a green light.

A third object of the invention is to provide a control system such that the lights controlling traffic on intersecting roads change over to a flashing amber in the event that red lights are simultaneously absent on the intersecting roads.

A fourth object of the invention is to provide an improved system such that the lights are controlled in dependence on the traffic density on one or more roads, for example in order to shorten the green light time on a road carrying little traffic.

A fifth object of the invention is to provide means to coordinate the operations of a group of control systems with the minimum of connections between the systems.

These and other objects of the invention are achieved by embodiments described hereinafter with reference to the figures of the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6 is a schematic diagram of a system for achieving the fifth object of the invention;

FIG. 7 is a schematic and block diagram showing one form of the decoder 8 and programmer 3 of FIG. 1; and

FIG. 8 is a signal and timing diagram illustrating an example of operation of the system of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT The control system for a set of groups of trafiic lights as illustrated in FIG. 1 is of the type comprising a clock which receives a control signal of given frequency and which delivers corresponding timing signals, a programmer which receives the timing signals and which delivers output signals representative of commands for switching traffic lights on and off, and a logic system which receives the output signals and which consequentially controls the operation of the power circuits for the lights. According to the invention, such a system is characterized in that it comprises a first counting clock 1 operating at a relatively low frequency F 1 and a second counting clock 2 operating at a relatively high frequency F2. Sources of clock pulses and 102 are shown, by way of example, for applying continuous trains of clock pulses to the counters l and 2 at frequencies F1 and F2. Preferably, the

counting clocks

1 and 2 are characterized in that each counts the clock pulses applied thereto up to the same maximum count number, but at different speeds given by their respective operating frequencies. The time for clock 1 to reach the maximal count number is the actual real time period of a complete cycle for green, amber and red lights and is a measure of real time. The different count outputs of the second counting clock 2 are respectively connected through a decoder 8 to inputs of a programmer 3, which forms, at two separate output circuits, 1 and 0 pulses for controlling a specific state of the traffic lights in a way which is predetermined for each value of the count of counting clock 2. The mentioned specific state of the traffic lights is preferably the on or off state of the green light in one traffic light group. Programmer 3 therefore provides a very rapid repetition of the control pulses on the two outputs of the programmer in correspondence with the accelerated time cycle of the counter 2. The control pulses from programmer 3 are positioned with respect to accelerated count provided by counter 2 as they must be given to control the traffic lights in real time.

The outputs of the two counting clocks l and 2 are respectively connected to corresponding inputs of a comparator 4. The comparator 4 is a conventional circuit which has a plurality of outputs each corresponding to a preselected value of the count shift between the counts of the two clocks. Among these outputs, there is only one input T0'at which a control signal is formed when there is no phase shift between the counters (i.e., the counters are in the same state). Two other outputs are T3 and T5" at which control signals are formed when the phase of clock 2 lags the phase of clock 1 by three and five counts respectively.

The logic system 5 is connected to the outputs of the programmer 3 and to the outputs of comparator 4, and operates in such a way that the output control pulses of the programmer 3 are transformed into control states (rectangular waves) in a bistable circuit located in logic circuit 5, which provides a very rapid representation of the signals from the control cycle and these control states are only taken into consideration for controlling purposes at the instants with no (or a predetermined) count shift between counting

clocks

1 and 2. Thus logic system 5 only uses the control states derived from the output pulses of programmer 3 when the real time count given by counting clock 1 has no (or a predetermined) count shift relative to rapid time count from clock 2. The commands delivered through rapid cycles by the programmer 3 are rendered operative by the comparator output signals, in a repetitive way. A spurious pulse could only change by one the number of rapid command pulses and would not be taken into consideration by the low speed power output circuits for the lights.

In the particular embodiment of the invention shown in FIG. 1, each clock comprises a first binary counter 1a, 2a, respectively, having four binary coded decimal (BCD) outputs, (conventionally referred to as the l, 2, 4, 8 outputs) at which signals are formed representing seconds of time, and a second binary counter 1b, 2b, respectively, having four BCD (1, 2, 4, 8) outputs at which control signals are formed representing tens of seconds. The decoder 8 is a BCD to decimal decoder. As illustrated in FIG. 7, the decoder 8 has ten outputs U to U9 and ten outputs D0 to D9. The decoder 8 receives the BCD signals at the four output circuits from the counter 2a representing seconds and converts them to a corresponding signal at one of outputs U0 to U9. The decoder 8 receives the BCD signals at the four output circuits from counter 2b representing tens of seconds and converts them to a corresponding signal at one of outputs D0 to D9.

In another embodiment of the invention, the decoder and clocks could be replaced with clocks which comprise a first binary counter la, 2a, respectively, directly providing the ten outputs U0 to U9 for seconds of time, and a second binary counter lb, 2b, respectively, directly providing the 10 outputs D0 to D9 for tens of seconds.

Preferably, the relatively high frequency F2 is very high in relation to the relatively low frequency F1, these two frequencies being, for example, respectively 30kI-IZ and lI-Iz. Thus, if clock 1 is considered as giving a real time cycle in which the 24th second, for example, is defined by a particular pulse at output 2 of counter 1b, and a pulse at the output 4 of counter la of the clock, the clock 2 gives an accelerated time cycle which is thirty thousand times faster than the real time cycle.

In accordance with the programming, the programmer 3 converts the clock pulses it receives and delivers output signals in the form of pulses representing the intervals of time between the commands for switching the lights on and off respectively.

Refer now to FIG. 7. FIG. 7 illustrates the decoder 8 in block form, showing the inputs and outputs therefrom. Also shown is the portion of the programmer 3 for controlling one group of lights 7. The programmer 3 includes for each group of lights 7, two pairs of ten inputs to one

output switch

30, 3b and 3c, 3d, respectively, corresponding to green-on and green-off control pulses. The switches in each pair select one connection out of the tens of seconds connections D0 to D9 (from decoder 8), and one connection out of the seconds" connections U0 to U9 (from decoder 8) respectively, and their outputs are fed to one of two AND gates 3f and 3g which form an output pulse whenever the rapid counting clock 2 counts the programmed count value as determined by the switches 30 to 30. For instance, if 05 seconds is programmed (i.e. switches 3b and 3a are connected to D0 and US) for green-on time and 35 seconds is programmed (i.e. switches 34' and 3c are connected to D3 and US) for green-off time, whenever the clock 2 counts 05, a green "on" control pulse appears on the 1 output of AND gate 3f of the programmer 3 and whenever the clock 2 counts 35, a green off control pulse appears on 0" output of AND gate 33 of the programmer 3. The switches may be electronic switches or may be mechanical or electromechanical rotary or sliding switches actuatable by hand or automatically.

A set of switches 3a to 3d and gates 3f and 3g (not shown) separately connected to outputs U0 to U9 and D0 to D9 is provided in programmer 3 for each group of lights 7.

Refer now to FIG. 2 which shows one embodiment of the logic system S. In the embodiment shown in FIG. 2, the logic system 5 which controls the operation of the lights comprises for each group of lights 7 a main bistable circuit 9 whose inputs are connected to the 1" and 0 outputs of the programmer 3 and whose outputs are connected to the inputs of a plurality of secondary bistable circuits 10a, 10b, 10c whose outputs are connected to the respective power circuits 6a, 6b, 60 for the lights 7.

The secondary bistable circuits 10a, 10b and 100 are triggered under control of signals at output circuits T0, T3 and T5 respectively. The output circuits from the main bistable circuit 9 are fed to corresponding inputs of each secondary bistable 10a to 100. The bistable 9 transforms the control pulses from programmer 3 into control states. The secondary bistables 10a, 10b and 100 make consequently a validation of the control states from the bistable 9 at their respective instants of triggering. The bistable 10a controls the green light power supply 6a. One of bistables 10b and 100 controls the amber light power supply 6b when the green light is off. The red light power supply 6c is controlled when the green and amber lights are off. In this manner, the green, amber and red lights 7a, 7b and may be sequentially energized in the recited order, one immediately after another.

In this application, the bistable circuits are said to provide control signals at 1 and 0 outputs when in l and 0 states respectively.

' By way of example, FIG. 2 shows the 1 output of bistable 10a connected to the control input of power supply 6a for the green light 7a; shows the 0 and 1 outputs, respectively, of bistables 10a and 10b coupled to an AND gate 104 which, in turn, has its output connected through a contact to a pole of switch 110 to the control input of power supply 6b for the amber light 7b; shows the 0 and 1" outputs, respectively, of bistables 10a and 10c coupled to an AND gate 106 which, in turn, has its output connected through another contact to a pole of switch 110 to the control input of power supply 6b; and shows output 1" of bistable 10a and the pole of switch l 10 coupled to the input of NOR gate 108 which has its output coupled to power supply tie for the red light 7c. Thus when bistable 10a is in a 1 state, only power supply 6a is controlled, thereby energizing the green light 7a. When bistable 10a is in a 0 state and bistable 10b in a 1 state and switch 110 connects gate 104 to power supply 6b, the amber light 7b is energized. When bistable 10a is in a 0 state and bistable in a 1 state and switch connects gate 106 to power supply 6b, then the amber light is also energized. When bistable 10a is in a 0 state and the gate 104 or 106 (to which the pole of switch 110 is connected) is not providing an output (as when corresponding bistable 10b or 100 is in a state), the NOR gate 108 controls power supply 60 causing the red light to be illuminated. To be explained, when switch 110 enables bistable 10b and gate 104 to control the power supply 6b, the amber light stays on longer than if bistable 10c and gate 106 does the control.

Thus for each group of lights 7, there is one set of switches 3a to 3d and one set of

bistables

9, 10a, 10b and 100 and power supplies 6a, 6b, and 60 connected as shown in FIGS. 2 and 7. The number of secondary bistable circuits can be reduced by providing one or more AND and/or OR gates in the logic system. In a simplified embodiment within the scope of the invention, the on-time of the amber light is given by a separate timing circuit actuated by the turning off of the green or amber lights and is included in the light power supply 6. There is no more need of T3 and T signals and of b and 100 bistable circuits. Further, the maximal count of clock 2 can be fixed independently of the predetermined maximal count of clock 1.

Consider now an example of the operation of the traffic control system. FIG. 8 is a wave-shaped diagram illustrating various control signals and the states of pertinent circuits described above. Assume that switches 3b and 3a of programmer 3 are set to 05, respectively, and switches 3d and 3c are set to 34. It is assumed herein that the counters l and 2 have a maximum count of 80. Also assume that the real time counter l is in state 34 and that the rapid counter 2 is going through its final sequence of counts before the real time counter 1 changes to state 35. When the rapid counter 2 reaches state 05, gate 3f is energized and provides a pulse at the 1 output which triggers bistable 9 to a 1 state. State 34 of the rapid counter 2 causes the comparator 4 to form a control pulse at the T0 output which confirms or strobes the 1 state of the bistable 9 into the bistable 10a. It should be noted that the first T0 pulse occurring during state 05 of the real time counter 1 triggered the bistable 10a into a 1 state where it has remained throughout states 05 through 34. As a result, power supply 6a energizes the green light 7a. Each T0 pulse has confirmed the 1 state of the bistable 10a. State 35 of the rapid counter 2 resets the bistable 9 to a 0 state. However, since it occurs after the T0 pulse,-it has no effect on bistable 10a.

Assume now that real time clock 1 goes to state 35. Bistable 9 is again in a 1 state between states 05 and 34 of the rapid counter 2. T0 now occurs during state 35 of the rapid counter 2 and hence during the 0 state of bistable 9. As a result, bistable 10a is now reset to a 0 state and hence turns off the green light.

Bistable 10c was triggered to a one state when real time counter 1 reached state 10 being triggered'by the first T5 pulse. Bistable 100 has remained in a 1 state. Bistable 10a is now in a 0 state and bistable 10c in a 1 state, therefore, gate 106 energizes power supply 6b which, in turn, energizes the amber light 7b.

Bistable 10c remains in a 1 state for 5 seconds, that is, until real time counter 1 reaches state 40. At this time, the T5 pulse resets the bistable 10c to a 0 state, disabling the power supply 6b and deenergizing the amber light 7b. At this point in time, neither the pole of the switch 110 nor the one output of bistable 10a is forming a control signal and, as a result, the NOR gate 108 energizes the power supply 6c which in turn energizes the red light 7c. This condition remains until the green light'7a is again energized when the bistable 10a is set to a 1 state during state 05 of the real time counter l. A shorter counter period can be programmed by changing switch 110 so that gate 104 is connected to the amber power supply 6b. To this end, bistable 10b is triggered to a 0" state for a phaseshift of 3 between counters l and 2 rather than 5 as for bistable 100.

When the operating cycle of the system is to include stop periods, i.e., intervals of time in the cycle, the duration of which can be lengthened or shortened to modify the lights, an auxiliary programmer is provided which defines the starting and end times of external control periods, said auxiliary programmer being connected to the clock so as to stop operation at normal clock frequency at the start of a period and cause the clock to operate with a control signal of a higher frequency than the normal operating frequency from an external restart command (manual or otherwise), so that the clock then practically instantaneously arrives at the end of the period in the corresponding state, the clock then operating again at normal frequency.

Refer now to FIG. 3 for one embodiment of the invention for this purpose. Two different control signals are needed. The first one, referenced S, is derived by a gate circuit 112 from 0 state of bistable 10a. The stop command on clock 1 is operative only until the S signal is indicating that the green light is off. The second control signal R controls the replacing of normal value F (1 Hz) of clock frequency F l with a higher value F (200 Hz for instance) which allows the acceleration of real time count whereby the total duration of .a cycle may be shortened. Without use of control signal R, the total duration of a cycle can be lengthened. For such unordinary operations, the system comprises an auxiliary programmer 1] controlled by second clock 2 and programmed in the same way as programmer 3, and a pair of auxiliary bistable circuits such as 12 and 12. The programmer 11 has a decoder similar to 8 and only one pair of switches similar to 3a, 3b, or 3c, 3d for delivering a pulse at a programmed count of clock 2, said pulse being the start of a stop period of clock 1, as explained hereafter. This pulse is fed as set command to bistable 12 which is reset by signal S. The signal S occurs when bistable 10a is in a-0 state and green light 7a is not on. Clock 1 being stopped, the state of the whole traffic line system associated to clock 1 is maintained. This stop of clock 1 is derived from the output control of bistable 12' which is transmitted to bistable 12. It will be recognized that the assembly of programmer ll, bistable 12, bistable 12, has the same circuitry as that of programmer 3, bistable 9 and bistable 10a. However, programmer 11 only provides one pulse which pulse defines the start of the stop period of clock 1. This is obtained through feeding the 0 output of bistable 12 to an AND gate 114 for controlling feeding of a source 122 of frequency F as frequency F1, to clock 1. When 12 is set to a 1" state indicating the start of a stop period, 12 is set responsive to a signal at T0 from comparator 4 and the AND gate 114 is inhibited. At the same time that the bistable is reset by feeding the 1 output of bistable 13 to the reset input of bistable 120, AND gate 116 is inhibited and cannot feed frequency F as frequency F1 to clock 1. At each time of the started stop period, a pulse R on the set input of bistable 120 may set it to the 1 output state which enables the AND gate 1 16 to feed frequency F as frequency F1 to clock 1. The frequency F is much higher than frequency F. As a result, the clock 1 counts rapidly up to the next green-off period which causes signal S to reset bistable 12' and shorten the time the green light is on. Each group programmer ll, bistable l2, bistable 12 provides a minimum duration of the green-on time period, after which it is possible to control at any time the end of said green-on time period. Preferably, a such group is provided for a zero minimal duration of greenon time period. The restart pulse R may be derived from a policeman with a pushbutton switch, a device for adapting the traffic light system, as described hereinafter with reference to FIG. 5, a coordinating system for a little group of intersecting roads or a centralized command system for a more extended supervision. It must be noted that among a plurality of minimum green durations, a selected one must be switched, after which minimum duration, a restart pulse R becomes operative. The selection of a minimum duration is done through activation of a programmer like 11, said programmer setting on its programmed count, the bistable 12. That is done in rapid time. Bistable 12 triggered with T selects out of the rapid time command from 12 the real time command corresponding to the present count of clock 1.

FIG. 4 relates to a system for controlling the operation of a set of groups of traffic lights on pairs of intersecting roads, characterized in that for each pair A of intersecting roads there is a corresponding pair of relays V, V', each controlled by the operation of the red light of a group of lights of one of the roads of the pair in such manner that the relay is energized when the group of lights is at red. Two normally open contacts C and C of the relays are connected in parallel in a conductor L so that the latter is open only if neither of the two relays are energized. The various conductors L are grouped in series into a general conductor J which is closed only if at least one of the groups of lights of each pair is at red. A source of power 126 and the coils of a relay P are serially connected in conductor J. Opening of the general conductor .1 causes relay P to be deenergized and activate a flash control unit 128 which in turn controls the flashing amber of each group,

of lights..

In the system illustrated, a matrix panel is used, having conductive lines 140. The horizontal conductive row lines are connected to the windings of the relays and the vertical column lines of conductive lines are related to the red lights of the groups. The electrical connections are made by switches or electrical contacts K which are selectively connected between the columns and lines. This matrix panel allows selective connection of contacts K to adapt the traffic control system to any complex situation of intersecting roads, especially when a main road is concerned, and the security of operation thereof.

By way of example, the state of any red light is detected and indicated by a circuit 146 (see FIG. 2) including a transformer in parallel with the light control element (Triac), the transformer delivering an ac. signal which is rectified to give a d.c. signal at 6c when the light is at red.

The state of a light can also be detected photoelectric cell system. 1

FIG. relates to a system for controlling the operation of a set of groups of traffic lights, characterized in by a neon that it comprises detection means D, e.g. a radar detector, to indicate the presence of a vehicle on at least one of the roads Z, a counter M associated with the detection means so that its operation is stopped for the period of each detection. The counter is adsociated with a programmer P when the counter reaches a given state which is adjustable by means of the programmer P and which corresponds to a given time of non-utilization of the road, delivers a pulse T which is used to produce a change of state of the traffic lights or restart the signal control equipment so that the lights are controlled in dependence on the traffic density on said road.

In short, the counter counts the intervals of time be tween the vehicles on the road and produces a change of state of the lights when the sum of the intervals reaches a predetermined and adjustable value corresponding to a given period of non-utilization of the road. If the road is insufficiently used, the operative period of the red lights on the road can thus be lengthened and vehicles can be allowed a longer period of movement on a more frequently used intersecting road. A signal D from detector D indicates when no vehicle is present (clock pulses from a local clock 30 are fed to an AND gate 132). Along with signal D, the output signal of gate 132 is transmitted for increasing the count of a binary counter M. The programmer P is programmably connected to output connections of the counter M, to sense their activation and feed the activation as a pulse T on its output.

When the detector D is used for adapting the greenon time period of the above described system, a programmer P is activated, thus providing a minimum green-on period, after which there is a stop period. The counter M is cleared as long as there is no stop period. At the beginning of the stop period, M begins to count up to the programmed value in P. When P senses this programmed count being reached, it gives a pulse T which is fed as signal R tothe circuits of FIG. 3 to restart the system and end the stop period very rapidly.

When the operation of a plurality of control systems is required to be adjustably controlled from a center of coordination, for instance a supervising computer, there is fed to each control system at least a command for stop period, and further restart, whereby the systems may be synchronized and separately controlled as to their respective offsets (shifts) and splits? (i.e. green-on duration timing).

Refer now to FIG. 3. When the operation of a plurality of control systems I, II, III, etc. is required to be coordinated, each such system comprises a clock l-I defining a time cycle for the operation of the system (FIG. 6). It is advantageous according to the invention to provide each system with means for stopping the operation of the clock of the system at a given time in the cycle, as described with respect to FIG. 3 and also to provide each system receiving at the same time as the other systems a command signal R for restoration of the operation of its clock and comprising means for rendering such command effective only after a selected interval of time. The restoration signal and its use is described with respect to FIG. 3.

Thus the various systems can be connected by a common conductor 134 to one of them, such as system I selected as the master system. The master system comprises means whereby the general command signal R for restoration of operation is given over the common conductor and is carried out by each slave system with an adjusted time shift. Thus, especially for start of a synchronization of traffic lights of a plurality of roads intersecting a main road, one of the control systems according to the invention acts as a master system and begins to operate, the other slave system beginning to operate with suitable time shifts.

The synchronization is further maintained by lock of the different clocks 1, with suitable count shifts, on the clock 1 of the master control system.

The traffic light control system according to the invention provides a predetermined basic cycle, the duration of which is given by count of clock 1, and the programming of which is given by programmer 3, which preferably controls the on/off state of green lights; a plurality of controllable means in programmer 11 for shortening or lengthening the on state of green lights (for instance); a special circuit for use in the case of insufficiently used roads; a manual control of lights; a possibility of coordination; and a flashing amber security.

Further, when using several traffic light control systems, it is possible to synchronize them automatically relative to one of them as a master and to realize easily a flashing amber security. It must be noted that the devices described hereabove may be interconnected in many different manners for controlling a traffic light assembly. Preferably,

common counting clocks

1 and 2 are used for two or more roads intersecting at one point. The set of lights for each road has a particular programmer 3 connected to the circuitry shown in FIG, 2. When the two directions on a road are given identical traffic light states, their lights can be connected directly to the outputs of a common group of bistables a to 100. However, any other combination made by a man skilled in the art and encompassed in the following claims is part of this invention.

Modifications as to detail and variants of the systems described hereinabove using functionally equivalent means may be made without thereby departing from the scope of the invention.

1 claim:

1. A system for controlling the operation of a set of groups of traffic lights comprising:

a first source of control signals of relatively low frequency;

a first clock having a time signal output;

means connecting said first source to said first clock;

a second source of control signals of relatively high frequency;

a second clock having a time signal output;

means connecting said second source to said second clock;

a programmer having command signal outputs;

means connecting said outputs of said second clock to said programmer, said programmer including means to convert time signals from said second clock to command signals at said programmer outputs for switching said lights;

a comparator;

means connecting said outputs of said first clock to said comparator;

means connecting said outputs of said second clock to said comparator;

said comparator including means for comparing the shift between the output signals of said clocks and having at least one output at which a signal is 10 formed corresponding to a preselected value of said shift;

a logic system having command signal outputs;

means connecting said command signal outputs of said programmer to said logic system;

means connecting said outputs of said comparator to said logic system, said logic system including means to render operative at said logic system outputs command signals delivered by said programmer only on receipt of signals from said comparator outputs; power circuits for said lights; and

means connecting said logic system command signal outputs to said power circuits.

2. A system according to claim 1 in which each of said clocks comprises at least one binary counter controlled by the respective source of control signals, and a decoder interposed in said means connecting said signal outputs of said second clock to said programmer.

3. A system according to claim 2 in which each of said clocks comprises a first binary counter having ten outputs for seconds of time and a second binary counter having 10 outputs for tens of seconds, the frequency of the first source being lHz so that seconds of clock 1 are real time seconds.

4, A system according to claim 1 in which said comparator has at least three outputs, corresponding respectively to a zero shift, a three position shift and a five position shift between the states of the two clocks.

5. A system according to claim 1, said logic system comprising for each group of lights, a main bistable circuit having inputs connected to said outputs of said programmer and having outputs, a plurality of secondary bistable circuits each having outputs, means connecting said outputs of said main bistable circuit to said secondary bistable circuits, and means connecting each of said secondary bistable circuits to a different output of said comparator whereby the contents of said main bistable circuit pass to whichever secondary bistable circuit is receiving an output signal from said comparator.

6. A system according to claim 1 comprising an auxiliary programmer having an output and which defines at least the starting point of external control periods in the normal cycle, means connecting said auxiliary programmer to the second clock, means connecting said output of said auxiliary programmer to said first clock to interrupt, said means connecting said first source to said first clock at the time of the start of said external control period, and another source of signals of a frequency higher than said frequency of said first source, a restart control, and means operated by said external restart control to connect said first clock to said other source of signals to advance said first clock rapidly to a state corresponding to the end of the external control period.

7. A system according to claim 6 including a pairzof bistable circuits, each having 1 and 0 outputs, each pair corresponding to a respective start of the external control period, means sensitive to said second clock and providing at an output of said auxiliary programmer a signal corresponding to a start of the external control period, means connecting said start output of said auxiliary programmer to an input of said auxiliary bistable circuit, the output of said first auxiliary bistable circuit being connected to the inputs of second auxiliary bistable circuits in said pair, at least one restart bistable circuit having 1 and inputs and l and 0 outputs, means feeding the 1 input of said restart bistable circuit with said restart control, means connecting said second auxiliary bistable circuit to said restart bistable circuit so that said restart bistable circuit has its 0 output activated when the 1 output of said second auxiliary bistable circuit is activated at said period, a first AND gate with inputs connected to the 0 outputs of said second auxiliary bistable circuit and to said first signal source, a second AND gate having an input coupled to the 1 output of a second auxiliary bistable circuit, an input coupled to the 1 output of said restart bistable circuit and an input coupled to said other source, and an OR gate the inputs of which are connected to the outputs of said AND gates and the output of which is connected as control input to said first clock.

8. A system according to claim 7 wherein each first auxiliary bistable circuit has its input controlling its 0 output state connected to means sensitive to a specific state of the traffic lights.

9. A system according to claim 6 wherein said auxiliary programmer has an output activating said pair of auxiliary bistables at the start of the external control period at the instant of a specific state of the traffic lights, enabling the duration of the last mentioned specific state to be modified under control of said programmer.

10. A system for controlling the operation of a set of groups of traffic lights on pairs of intersecting roads each traffic light having at least red and amber light circuits, the system comprising for each pair of intersecting roads a corresponding pair of relays, each relay having contacts which are open when the relay is in a first state and closed when the relay is in a second state, means for indicating a red light circuit is energized, means responsive to a red light circuit indication for the group of lights on one road of said pair of roads for controlling the corresponding relay of the pair such that the relay is in the second state when the respective group of red light circuits is energized, the contacts of said pair of relays being disposed in parallel in a conductor such that the conductor is interrupted only when neither relay is in said second state, the conductors for all the pairs of roads being disposed in series in a circuit which is closed only when at least one of the groups of red light circuits is energized, means for triggering a flashing signal in the amber light circuit of all said groups when said circuit is interrupted and a matrix panel including electrical row lines connected to the windings of said relays and crossing electrical conductive column lines coupled to the indication means for the red lights of said groups and means for selectively electrically interconnecting said row lines and column lines.

11. A system for controlling the operation of a set of groups of traffic lights for intersecting roads, comprising:

means for detecting the presence of a vehicle on at least one of said roads;

a counter;

means connecting said detecting means to said counter to interrupt the operation of said counter for the duration of each detection;

a programmer;

means connecting said programmer to said counter,

said programmer including means which, when said counter reaches a predetermined state, is adjustable by said programmer and which corresponds to a predetermined time of non-utilization of the road, delivers an output signal; and

means responsive to said output signal to control the state of said traffic lights.

12. A system as defined in claim 1 wherein there is a plurality of said systems and for coordination of said systems, each of said systems comprising means for stopping its said first clock at a given time in the cycle, means for receiving simultaneously with the other control systems a command signal for restarting said first clock, and means for rendering said command signal effective only after a time interval preselected for each control system.

UNITED STATES PATENT OFFICE CERTIFICATE OF] CO RRECTWN Patent No. 3,754,210 Dated, 21, 1,973

Inventor(s) Jean Claude Preti It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

C01. 2-, line 51, "in ut" should read output-- Col. 6, line 63, "13 should read --12--. C01. 8, line 5, "edsociated" should "read-"associated".

Signed and sealed this 26th dayof March 1974'.

(SEAL) Attest:

EDWARD M.FLI-ITCHER,JR. C. MARSHALL D'ANN Commissioner of Patents Attesting Officer

Claims

1. A system for controlling the operation of a set of groups of traffic lights comprising: a first source of control signals of relatively low frequency; a first clock having a time signal output; means connecting said first source to said first clock; a second source of control signals of relatively high frequency; a second clock having a time signal output; means connecting said second source to said second clock; a programmer having command signal outputs; means connecting said outputs of said second clock to said programmer, said programmer including means to convert time signals from said second clock to command signals at said programmer outputs for switching said lights; a comparator; means connecting said outputs of said first clock to said comparator; means connecting said outputs of said second clock to said comparator; said comparator including means for comparing the shift between the output signals of said clocks and having at least one output at which a signal is formed corresponding to a preselected value of said shift; a logic system having command signal outputs; means connecting said command signal outputs of said programmer to said logic system; means connecting said outputs of said comparator to said logic system, said logic system including means to render operative at said logic system outputs command signals delivered by said programmer only on receipt of signals from said comparator outputs; power circuits for said lights; and means connecting said logic system command signal outputs to said power circuits.

3. A system according to claim 2 in which each of said clocks comprises a first binary counter having ten outputs for seconds of time and a second binary counter having 10 outputs for tens of seconds, the frequency of the first source being 1Hz so that seconds of clock 1 are real time seconds.

4. A system according to claim 1 in which said comparator has at least three outputs, corresponding respectively to a zero shift, a three position shift and a five position shift between the states of the two clocks.

7. A system according to claim 6 including a pair of bistable circuits, each having 1 and 0 outputs, each pair corresponding to a respective start of the external control period, means sensitive to said second clock and providing at an output of said auxiliary programmer a signal corresponding to a start of the external control period, means connecting said start output of said auxiliary programmer to an input of said auxiliary bistable circuit, the output of said first auxiliary bistable circuit being connected to the inputs of second auxiliary bistable circuits in said pair, at least one restart bistable circuit having 1 and 0 inputs and 1 and 0 outputs, means feeding the 1 input of said restart bistable circuit with said restart control, means connecting said second auxiliary bistable circuit to said restart bistable circuit so that said restart bistable circuit has its 0 output activated when the 1 output of said second auxiliary bistable circuit is activated at said period, a first AND gate with inputs connected to the 0 outputs of said second auxiliary bistable circuit and to said first signal source, a second AND gate having an input coupled to the 1 output of a second auxiliary bistable circuit, an input coupled to the 1 output of said restart bistable circuit and an input coupled to said other source, and an OR gate the inputs of which are connected to the outputs of said AND gates and the output of which is connected as control input to said first clock.

11. A system for controlling the operation of a set of groups of traffic lights for intersecting roads, comprising: means for detecting the presence of a vehicle on at least one of said roads; a counter; means connecting said detecting means to said counter to interrupt the operation of said counter for the duration of each detection; a programmer; meAns connecting said programmer to said counter, said programmer including means which, when said counter reaches a predetermined state, is adjustable by said programmer and which corresponds to a predetermined time of non-utilization of the road, delivers an output signal; and means responsive to said output signal to control the state of said traffic lights.