US3299401A

US3299401A - Traffic signal controller

Info

Publication number: US3299401A
Application number: US503674A
Authority: US
Inventors: Norman A Bolton
Original assignee: General Signal Corp
Current assignee: SPX Corp
Priority date: 1965-10-23
Filing date: 1965-10-23
Publication date: 1967-01-17
Anticipated expiration: 1984-01-17

Description

Jan. 17, N BQLTON TRAFFIC SIGNAL CONTROLLER 6 Sheets-5heet Ll Original Filed Sept. 12, 1963 O N TO R m 0 mm mopowdm m2; wL w 35m 205 m A B m A. H N m 55m mzia ZOE ZOO ZmDPmm 2mm mEEa . mime mama I I I... I I I I oznomoxgm I I mm mo 8 M56 ZUEC. m 0E hm P29 024 Oh .Jan. 17, 1967 N. A. BOLTON TRAFFIC SIGNAL CONTROLLER 6 Sheets-Sheet Original Filed Sept. 12, 1963 zwwm mON

VIII-ll 4 0m .CDOEO JOKFZOO 20mm ll' lllllll llilll' wON wmm

wzm o I EGGE w OE Jan. 17, 1967 N. A. BOLTON TRAFFTC SIGNAL CONTROLLER Original Filed Sept. 12, 1963 6 Sheets-Sheet 2 FIG.8v

CONTROL CIRCUITS 33 $R N L REG IST ER \I 5E T I I I I I I I I .1

RF GENERATOR I99 FROM INTERVAL DRIVER CIRCUIT 2 FIG. 7

CONNECTION TO INTERVAL TIME SELECTOR 22 AND COUNTERS IOANDII l/INTERVAL DRIVER INVENTOR. NA. BOLTON QLWMW HIS ATTORNEY CONNECTION TO CONTACTOR CONTROL REGISTER 32 Jan. 17, 1967 N. A. BOLTON 3,299,401

TRAFFIC SIGNAL CONTROLLER Original Filed Sept. 12, 1963 6 Sheets-Sheet 5 FIGS) SIGNAL OPERATION CHART SIGNAL SIGNAL ALLOCATION TO STEPS OF INTERVAL TIMING REGISTER SIGNALS PECT A5 030 CSI C32 C33 C34 C35. C36 03? GREEN X X SA YELLOW X RED I X X X X y X GREEN X X SB YELLOW X RED X X X X X Sp WALK X I WAIT X X X X X X X WALK X SP2 WAIT X X X X X X X LEGEND X DENOTES SIGNAL OPERATED DURING CORE OPERATION TO ONE SECOND TO TEN SECOND COUNTER IO COUNTER II 4\.

Ol23456789 o|2s45s1 9 FROM INTERVAL DRIVER CIRCUIT (FIG.6)

F I G. IO INVENTOR.

Y NA. BOLTON HIS ATTORNEY United States Patent 3,299,401 TRAFFIC SIGNAL CONTROLLER Norman A. Bolton, Scottsville, N.Y., assignor to General Signal Corporation, Rochester, N.Y., a corporation of New York Continuation of abandoned application Ser. No. 308,597, Sept. 12, 1963. This application Oct. 23, 1965, Ser No.

9 Claims. (Cl. 340-41) This application is a continuation of my prior application Ser. No. 308,597, filed September 12, 1963, now abandoned. This invention relates to a highway traffic signal controller, and, more particularly, pertains to an electronic controller of the pretimed type in which the signal cycle length and the individual time intervals for a traffic signal are measured electronically.

At an intersection of conflicting streets, it is usually desired to allot a definite portion of the predetermined trafiic signal cycle to each of the different conflicting streets at the intersection. During each such portion, the green traflic signal is operated for the corresponding street while the stop trafiic signal is operated for all other streets at the intersection. Moreover, a plurality of intersections may be interrelated by having the periods of operation of the green traffic signal for at least one phase of trafiic movement interdependent to provide, for example, continuous trafiic movement along that phase and through the plurality of intersections.

It is usual in pretimed trafiic signal controllers to intermittently drive a cam shaft to its different positions in each of which a different combination of trafiic and pedestrian signals are operated. The time intervals between intermittent operation of the cam shaft constitute the various portions of the signal cycle and these time intervals are usually measured by the time required to mechanically move a dial through a plurality of preselected positions. Mechanical alterations must be made to such a controller for changing the time intervals and signal cycle length which may contribute further mechanical problems in addition to the normal mechanical problems encountered during usage.

It is contemplated by the present invention to provide a pretimed trafiic signal controller employing solid-state components which overcomes the mechanical limitations of the cam shaft type of system. More specifically, it is proposed herein to provide electronic control for the different portions of a traffic signal cycle in which different combinations of trafiic and pedestrian signal indications are operated at an intersection for the several different directions of traffic movement. For operating each different combination of trafiic and pedestrian signals, it is proposed to provide an electronic step-by-step means capable of cyclic operation through its different steps in a predetermined time period. In each step, a multi-aperture ferrite core is operated for controlling the combination of traffic and pedestrian signals allotted to that step of the signal cycle.

The time interval that the electronic step-by-step means remains on each of its different steps is measured by a time measuring means. More specifically, the time measuring means is operable to measure a plurality of time intervals responsive to input alternating current line energy having a frequency of 60 cycles per second. Gating means are provided for determining when a time interval has been measured by the time measuring means acc0rding to the step on which the electronic step-by-step means is then operating for advancing the step by-step means to its next step and also returning the time measuring means to a common reference time from which all time interval measurements are initiated. The time measuring means utilizes multi-aperture ferrite cores which are "ice operated responsive to the input of alternating current line energy of 60 cycles per second frequency to provide the plurality of time interval measurements for the different steps of the electronic step-by-step means.

It is further contemplated in the proposed embodiment that the traffic signal cycle and at least several of the individual time intervals for the traffic signals at the intersection can be controlled from a remote control station over a communication channel so that signalling at the intersection may be coordinated with one or more adjacent intersections. It is proposed in the present invention to provide gate means responsive to an incoming coordinating signal according to a particular step in which the electronic step-by-step means is then operating for altering the normal pretimed traffic signal cycle of the controller. A system of control for so operating the present trafiic signal controlled may be of the type shown and described in the pending application Ser. No. 239,714, filed on November 23, 1962, by I. H. Auer, Jr. et al.

Thus one object of this invention is to provide a traffic signal controller including an electronic interval timing register operable step-by-step through its different steps and maintained on each such step during the measurement of a time interval allotted to that step.

Another object of this invention is to provide a traffic signal controller including electronic time measuring means for measuring a plurality of time intervals each of which is allotted to a different combination of traffic and pedestrian signal display indications.

Another object of this invention is to provide a traffic signal controller of the pretimed type which has its different time intervals measured electronically, but which may be readily varied as required for diverse operating conditions without the use of moving parts.

Another object of this invention is to provide a traffic signal controller which utilizes solid-state components throughout for providing an efficient and durable controller of the pretimed type having accurately timed traffic signal cycles and individual time intervals thereof.

Other objects, purposes and characteristic features of this invention will be in part obvious from the accompanying drawings and will in part be pointed out as the description of the invention progresses.

In the description of the invention which follows, reference will be made to the accompanying drawings in which:

FIG. 1 illustrates diagrammatically and in block form one embodiment of this invention;

FIG. 2 illustrates diagrammatically a specific form of a driver circuit operable from an external trigger;

FIG. 3 illustrates diagrammatically the driver circuit of FIG. 2 operable from an internal trigger;

FIG. 4 illustrates diagrammatically one form of a divider register employing multi-aperture cores;

FIG. 5 illustrates diagrammatically one form of a second time register employing multi-aperture cores;

FIG, 6 illustrates diagrammatically one form of an interval timing register employing multi-aperture cores and their connection to interval driver circuits;

FIG. 7 illustrates diagrammatically a specific form of an interval driver circuit employed in the embodiment of this invention;

FIG. 8 illustrates diagrammatically one form of a contactor control register employing multi-aperture cores;

FIG. 9 is a signal operation chart for indicating the combination of traffic and pedestrian signals operated on each step of the interval timing register shown in FIG. 6, and

FIG. 10 is an illustration of a typical interval time selector.

It is contemplated that the present invention be employed to operate the traffic and pedestrian signals at an intersection of a main street or artery and one or more cross streets. For purposes of discussion herein, the main street or artery may be referred to as phase A having the trafiic signal designated SA and the pedestrian signal designated SP1, while the cross street may be referred to as phase B having the traflic signal designated SB and pedestrian signal designated SP2, as suggested in the block diagram of FIG. 1.

Referring now to FIG. 1, each of the traffic signals SA and SB illustrated includes conventional proceed, stop and traffic clearance signals labeled respectively G, R and Y. The pedestrian signals SP1 and SP2 as illustrated include a WALK-DONT WALK signal display. The individual time intervals that the trafiic and pedestrian signals are operated are dependent upon selections made to a counting means including a one second counter and a ten second counter 11. Each of these counters 10 and 11 includes a plurality of steps which together operate to provide a recurring cycle time period in response to the incoming line circuit frequency of 60 cycles per second. In the present embodiment, it is suggested that each of the counters 10 and 11 include ten steps in order that the operation of the counters 1t) and 11 produce a cycle time period of 99 seconds. As will become more apparent from the detailed description of this invention infra, the number of steps of each of the counters may be altered such that the cycle time period may be shortened or lengthened as desired.

The counter 10 is operated between its different steps upon receiving input drive energy from a driver 13 Which provides a one pulse-per-second output. The ten second counter 11 is operated between its successive steps upon receiving an input pulse from a driver 14. The driver 14 receives its input from the one second counter 10 each time that it is operated to its tenth step. The driver 14 thus provides an output once every ten seconds or six pulses per minute.

Driver 13 is operated once per second by an input which is derived from the 60 cycles per second line frequency. More specifically, the line frequency is applied to a pulse shaper circuit 15 which provides at its output a pulse of energy for each cycle of input line energy, or 60 pulses per second. The 60 pulses per second is applied to a driver 16. The 60 pulses-per-second output of driver 16 is applied to a divider 17 which provides one output pulse for every six input pulses. In other words, divider 17 provides ten output pulses for every 60 input pulses in the time of one second. Each of the output pulses from divider 17 is applied to a driver circuit 18 which couples the pulses to a divider i9. Divider 19 operates to provide one output pulse for every ten input pulses in the time of one second. The frequency of 60 cycles per second is thus changed to a one pulse per second output which is applied to the one second counter 10.

The counters 1t and 11 together comprise a digital counter which provides an output to advance register one step each time a particular count is reached, with the particular count being selected by selector 22 in accordance with the then-operated step of register 25. During the entire cycle time period of, for example, 99 seconds, an output from each of the counters 10 and 11 corresponds to a selection point determined by the interval time selector 22. The outputs of the counters 10 and 11 are selectively connected by the interval time selector 22 to interval driver circuit 23 for determining the time length of different time intervals in each of which different combinations of the trafiic and pedestrian signals are operated.

The interval time selector 22 may, for example, be a conventional contact type of selector employing, for example, push buttons, pins, or the like which may be quickly attached or detached for selecting desired outputs of the time registers 10 and 11.

The interval driver circuit 23 receives successive inputs from an interval timing register 25 during the traffic signal cycle for denoting the different individual time intervals wherein a different combination of the traffic and pedestrian signals are operated. More specifically, the interval timing register 25 includes a plurality of different steps through which the register 25 is operated step-by-step at intervals determined by the selections made by selector 22 of the outputs of the second time counters 10 and 11.

When the second time counters 10 and 11 are operated to a time selected by time interval selector 22, an output from each of the time counters 10 and 11 is applied to an AND gate 27 which provides an output for resetting the time counters 10 and 11 to a 00 timing condition and triggering an advance driver 29.

Advance driver 29 receives its trigger input during the time that the second time counters 1t and 11 have been operated to time registering steps corresponding to selections made by interval time selector 22 according to the operating step of the interval timing register 25. Advance driver 29 upon being triggered produces an output for operating the interval timing register 25 from its operating step to a successive step wherein a different combination of trafiic signal indications is provided.

In each operating step of the interval timing register 25, a pulsed input is supplied to the interval timing register 25 from a control circuit 30 so as to cause the register 25 to provide a pulsed output for that step. Control circuit 30 is operated in response to the operation of divider 17 when operating on a selected step thereof. Control circuit 30 also supplies an input to advance driver 29 which acts to reset advance driver 29 after it has received a trigger input for causing the interval timing register 25 to be advanced.

On each step of the interval timing register 25, the pulsed output is provided to drive an interval driver included with interval driver circuit 23 corresponding to the operating step of the interval timing register 25. The interval driver for the operating step then controls a contractor control register 32 which operates to selectively control signal control circuits 33 for operating a predetermined combination of traffic and pedestrian signals allotted to the operating step of the interval timing register 25.

In the above generalized description, the interval timing register 25 remains on each of its steps for a predetermined time interval depending upon the operation of the second time counters 1t] and 11 and the selections of their outputs by interval time selector 22 as described. If, however, it is desired to operate the traffic signals SA and SB as well as the pedestrian signals SP1 and SP2 in a coordinated system, a background signal for either phase A or phase B may be applied over a communication channel as suggested in the above-mentioned Auer application, Ser. No. 239,714 to the interval driver circuit 23 and to a gate and readout circuit 35.

The interval driver circuit 23 includes an interval driver corresponding to each of the steps of the interval timing register 25 wherein the green signal display for phase A or phase B is provided. One such interval driver is responsive to a phase A background signal, while the other interval driver is responsive to a phase B background signal when so selected. During the interval that the interval timing register 25 is operating on a corresponding step and before the corresponding phase A or phase B background signal is applied to the gate and readout circuit 35, the green signal display for the corresponding phase is continuously operated. However, upon reception of the corresporiding background signal, register 25 is advanced from its operating step wherein the green signal display is operated for the corresponding phase to a next step thereof. More specifically, the gate and readout circuit 35 then operates to reset the

dividers

17 and 19 as well as the second time counters 10 and 11 to respective steps allotted to the Zero step to operate advance driver 29 which is effective to advance interval timing register 25 from its operating step to a next step thereof.

In FIGS. 2 through 8, typical circuits employing single and multi-aperture ferrite cores are shown for the purpose of providing a better understanding of the detailed operation of the block diagram of FIG. 1. The typical circuits respectively illustrated in FIGS. 2 through 8 will be described separately hereinafter.

Referring now to FIG. 2, a typical driver circuit operable from an external trigger is shown. More specifically, the driver includes two single aperture cores C1 and C2. Each of the cores C1 and C2 includes a drive winding D, a set winding S and a readout winding R0. The driver windings D for cores C1 and C2 are serially connected to input trigger terminals which may be connected to the line circuit referred to in the block diagram of FIG. 1.

The set winding S for core C1 is coupled through a diode 40 and a four-layer diode 41 to a common connection of a resistor 42 and capacitor 43. energy is coupled through priming minor apertures included with multi-aperature cores of the register or counter with which the driver is employed and a coil 44 to one side of resistor 42. The set winding S of core C1 is further coupled to energy through driver apertures of the evenpositioned cores in a register and through a coil 46 and a resistor 47. The set winding S of coil C2 has one side thereof coupled through a diode 49 and a four-layer diode 50 to the common connection of resistor 42 and capacitor 43. The other side of the set winding S is coupled to energy through the drive apertures of the odd-positioned cores in a register and through the coil 46 and resistor 47. The readout winding R0 of coil C1 is connected in shunt with diode 49, while the readout winding R0 of core C2 is connected in shunt with diode 40.

In operation, capacitor 43 is charged through the circuit including the priming apertures of cores included with a register for priming those cores when capacitor 43 is charging. Each of the cores C1 and C2 provides an output on its readout winding RO provided that it has been set by current flowing through the set winding S and upon receiving pulsed energy on its drive winding D.

Initially, cores C1 and C2 are respectively set and cleared upon application of a energy pulse through a push button 52 when actuated. More specifically, in the non-actuated condition of button 52, a capacitor 45 is charged through a coil 47 and through the button 52. Upon actuation of button 52, the capacitor 45 is discharged through the coil 47, button 52 and a diode 48 through the apertures of the cores C1 and C2 as well as through set apertures of other cores to be described hereinafter, to

Upon application of pulsed energy to the trigger circuit which is applied through the drive windings D of cores C1 and C2, only core C1 provides an output on its readout winding R0. The output energy is such that diode 49 is back biased while the breakover voltage for the four-layer diode 50, diode 49, the set winding S of core C2, the drive windings of the odd-positioned cores in an associated register, coil 46, resistor 47, to causing core C2 to be set. The four-layer diode 50 remains in its conductive condition as long as the current flowing therethrough is greater than its holding current. Shortly after the current through the four-layer diode 50 falls below its holding current for a short time interval, diode 50 reverts to its blocking state. Capacitor 43 is then again charged through its circuit described above.

Upon receiving the next energy pulse in the trigger circuit and applied to the drive winding D of cores C1 and C2, only the readout winding R0 of core C2 is provided with an output which backward biases diode 40 while additionally causing the voltage across the fourlayer diode 41 to be increased to its breakover voltage causing it to conduct. Core C2 is also cleared. Capacitor 43, now charged, is discharged through the circuit including the four-layer diode 41, diode 40, the set winding S of core C1, the drive windings of the even-positioned cores for an associated register, the coil 46, re-

sistor 47, to The current flowing through this circuit causes the core C1 to be set. Upon the current flow caused by the discharge of capacitor 43 being reduced below the holding current of the four-layer diode 41, such diode 41 reverts to its blocking state again permitting the capacitor 43 to be charged through its charging circuit.

For successive input trigger pulses, the cores C1 and C2 are alternately operated to provide driving energy through the drive windings of the oddpositioned and even-positioned cores of an associated register. Prior to the time that energy is applied to either the odd-positioned or even-positioned cores, however, priming energy is also coupled through the priming apertures of the associated register in that they are included in the charging circuit of capacitor 43.

Referring now to FIG. 3, a driver is illustrated similar to the driver of FIG. 2 except that it includes an interval triggering circuit which may be operated, for example, by the output core of an associated register. The interval trigger circuit includes a transformer T1 through which input pulsed energy is applied to a circuit including a four-layer diode 54, a diode 55, a coil 56 and two

resistors

57 and 58. Resistor 57 is connected at one end thereof to energy and further connected to a capacitor 69 which has its opposite side coupled to the drive windings D of cores C1 and C2 and to the secondary of the transformer T1 through resistor 58 and coil 56. The capacitor 59 is charged through the circuit described including the drive windings D of cores C1 and C2 and discharged through the circuit including the four-layer diode 54 upon conduction thereof.

In operation, the incoming pulsed energy is applied through transformer T1 to one side of the four-layer diode 54, each pulse of which causes the breakover voltage of the four-layer diode 54 to be exceeded causing conduction thereof. Capacitor 59 is thus discharged through the circuit including the four-layer diode 54 and the drive windings D of cores C1 and C2. The core then in its set condition is operated to provide an output on its readout winding R0 as described for the driver of FIG. 2 for causing the opposite core to be operated to its set condition.

Referring now to FIG. 4, a typical divider is shown which includes ten cores C4-C13. Each of the cores C4-C13 is a multi-aperture ferrite core. In particular, core C4 includes four

minor apertures

62, 63, 64 and 65. Each of the cores C5-C13 includes two minor apertures, these being respectively 66 and 67 for core C5, 68 and 69 for core C6, 71 and 72 for core C7, 74 and 75 for core C8, 76 and 77 for core C9, 79 and 80 for core C10, 82 and 83 for core C11, 84 and 85 for core C12, and 87 and 88 for core C13. A winding couples each of the cores C4-C13 through each of its two minor apertures to two adjacent cores. For example, winding 90 couples core C4 through its minor aperture 64 to core C5 through its minor aperture 66. Winding 92 couples core C5 through its minor aperture 67 to core C6 through its minor aperture 68. Each such winding is provided for transferring operation from one core to an adjacent core when a given core receives a prime input and then a drive input.

The divider of FIG. 4, being typical includes a minor aperture 65 for core C4 thereof. A set Winding is threaded through this minor aperture 65, and this set winding is considered to be in the circuit shown in FIG. 2 for manually setting core C1 and clearing core C2. The purpose of so including minor aperture 65 of core C4 in this manually controlled circuit is to set the core C4 for operation when it receives a drive pulse. The terminals X and X" are assumed to be serially connected in the manual starting circuit shown in FIG. 2.

The prime input to the core C4C13 is provided when capacitor 4-3 of the driver shown, for example, in FIG. 2 is charged as described above. The prime winding is threaded through one of the two minor apertures employed with a transfer winding for each core. For ex ample, the prime winding is threaded through minor aperture 64 of core C4 and minor aperture 67 of core C5.

The cores C4-C13 include respective major apertures 1011-109. The major apertures of the odd-positioned cores C4, C6, C7, C and C12 are threaded by the circuit including the set winding S of core C2 of the driver shown in FIG. 2, while the major apertures of the even-positioned cores C5, C7, C9, C11 and C13 are threaded by the circuit including the set winding S of core C1 in the driver circuit of FIG. 2. In addition, the major apertures of the cores C5C13 and minor aperture 63 of core C4 are included in a circuit where a clear input is provided in response to the reception of a background signal for either phase A or phase B as described above.

In operation, the divider first receives a set input upon actuation of button 52 shown in FIG. 2 for setting core C4. The capacitor of its associated driver circuit is charged upon application of energy to the circuits which causes a prime input to be supplied to the respective minor apertures of the cores C4-C13. Core C4 then receives a drive input through its major aperture 101 responsive to the operation of its driver circuit for operating the core C4. For successive prime and drive inputs, transference of operation between adjacent cores is effected in a sequential manner in that a prime input followed by a drive input for the operating core causes a readout from a minor aperture thereof to be given for setting the adjacent core. For example, when core C4 receives its prime input coupled through its minor aperture 64, its set input coupled through minor aperture 65 and its drive input coupled through its major aperture 101), a readout pulse is taken from minor aperture 64 and applied over wire 90 to minor aperture 66 of core C5 for setting core C5.

Referring now to FIG. 5, a second time counter is diagrammatically illustrated. The second time counter includes ten multi-aperture ferrite cores designated C15 C24. Each of the cores C15-C24 includes two minor apertures each of which is coupled through a winding to an adjacent core through its minor aperture. For example, core C16 includes

minor apertures

112 and 113 which are coupled respectively to cores C15 and C17. More specifically, core C16 is coupled at its minor aper ture 112 to core C15 at its minor aperture 114 over a wire 115. Core C16 is further coupled at its minor aperture 113 to core C17 at its minor aperture 117 over a Wire 113. One of the two minor apertures employed for transfer of operation for each of the cores C15-C24 is included in the charging circuit for the capacitor 43 in the driver circuit as shown in FIG. 2 and upon charging of the capacitor 43, a prime input is applied to such minor apertures. For example, minor aperture 114 of core C1 5 and minor aperture 113 of core C16 are included in the charging circuit of capacitor 43.

Core C15 of the second time counter includes a minor aperture 121) and includes a winding coupled thereto which is connected by its terminal X and X" in the manually operated circuit shown in FIG. 2 for setting the core C15. Core C15 is initially operated to its set condition upon actuation of button 52 as described above. Thereafter, core C15 is operated to its set condition upon receiving an input on the winding coupled to minor aperture 121 upon transference of operation from core C24.

The major apertures of the cores C15-C24 are included in the respective circuits for operating the cores C1 and C2 of the driver shown in FIG. 2 to set conditions. More specifically, the major apertures for cores C15, C17, C19, C21 and C23 are included in the circuit for operating core C2 to a set condition, such cores being the oddpositioned cores. The major apertures of cores C16, C18, C20, C22 and C24 are included in the circuit for operating core C1 to a set condition, such cores being the even-positioned cores. The prime input followed by the drive input relative to an operating core (having been operated to a set condition) in the second time counter as provided by an associated driver causes transference of operation between that operating core to a successive core.

The frequency with which transference of operation occurs between the cores C14-C24 of the second time counter depends upon the frequency of pulsed energy inputs from the driver circuit. As described with reference to the block diagram of FIG. 1, the driver 13 provides a one pulse-per-second output which is applied to the one second time register 11 Thus, transference of operation between the cores of the counter 10 occurs once per second. Moreover, the driver 14 provides six pulses per minute at its output or one pulse every ten seconds. Such one pulse per ten seconds causes transference of operation between respective cores in the ten second time counter 11.

Each of the cores C15-C2 includes a third minor aperture which operates to provide an output to AND gate 27 when the second time counter is operated to the condition corresponding to the selection made in the interval time selector 22. For example, such third minor aperture for core C16 is designated 131. Each of the third minor apertures has an input winding threaded therethrough which is connected to the interval time se lector 22 and further connected to (-i-) energy. Each such third minor aperture also includes a readout winding such as, for example, readout winding 133 threading minor aperture 131 of core C16 for coupling such third minor aperture to AND gate 27 through a diode, these diodes for the cores C15-C24 being respectively designated 135-144. Each major aperture of the cores C16 C24 such as major aperture of core C16 and minor aperture 146 of core C15 is threaded by a wire over which a clear or reset input is applied from AND gate 27 or from a background signal communication system as will be more fully described infra.

The second time counter shown in FIG. 5 is considered to be typical of the one second time counter 10 and the ten second time register 11. In this connection, the concurrent application of a positive-going signal input to AND gate 27 from an operating core in each of the time registers 11) and 11 causes AND gate 27 to provide an output which is applied through minor aperture 146 of core C15 and the major apertures of cores C16-C24 of the cores in both time counters 10 and 11 as a clear input for resetting purposes.

In operation, the second time counter of FIG. 5 is operated successively between its different cores ClS-C24 in a cyclic manner according to the frequency of prime and drive inputs applied thereto as mentioned above. Operation of the second time counter to a condition wherein an operating core corresponds to the selected position of the interval time selector 22 causes an output signal to be supplied through the readout winding to AND gate 27. More specifically, the odd or even drive input to driver 19 is caused by operation of driver 18 is also threaded through the third minor aperture of the operating core in the second time counter causing an output signal on its readout winding when that core is operated. It is only when both time counters have operating cores corresponding to the selections made in the interval time selector 22 that concurrent readout signals occur to cause AND gate 27 to provide an output.

The output from AND gate 27 is applied to the cores included with each of the time registers 10 and 11 through the major apertures thereof for clearing such cores and further applied to advance driver 29 as a trigger input for advancing the interval timing register 25, as described generally above.

Referring now to FIG. 6, one embodiment of an interval timing register is shown which employs multiaperture ferrite cores C30C37 and further shows their individual connection to respective interval drivers 18 included with interval driver circuit 23. Each of the cores C3i)C37 includes two minor apertures each of which is included in a transfer circuit provided for that core. For example, core C31 includes

minor apertures

150 and 151. Minor aperture 150 of core C31 is coupled to core C30 at minor aperture 153 thereof over a coupling wire 154. Minor aperture 151 of core C31 is coupled to core C32 at minor aperture 156 thereof over coupling wire 157. Similar coupling arrangements are made between minor apertures of the remaining cores. A prime input is applied through one of the two minor apertures used in the transference circuit to an adjacent core such as, for example, minor aperture 151 of core C31.

Core C30 also includes a minor aperture 161 which may be used for the purpose of initially setting core C30 by serially coupling minor aperture 161 at terminals XX" to the manually controlled circuit shown in FIG. 2. Thereafter, core C30 is operated to its set condition upon transference of operation from core C37 to core C30 through the readout winding 163 coupled to minor aperture 164 of core C30.

In FIG. 6, the major apertures of cores C30, C32, C34 and C36 such as, for example, major aperture 160 of core C30 are included in the circuit for operating core C2 of the driver shown in FIG. 2 to a set condition. Similarly, the major apertures of cores C31, C33, C35 and C37 such as, for example, major aperture 162 of core C31 are included in the circuit for operating core C1 of the driver circuit shown in FIG. 2 to set condition as described above. The transference of operation between the cores C30-C37 occurs responsive to the prime and drive inputs supplied from advance driver 29 described with reference to FIG. 1.

Each of the cores C30-C37 in FIG. 6 includes a minor aperture which is intermittently primed and driven to provide an output winding coupled thereto a succession of pulses which are applied to an associated interval driver included with interval driver circuit 23. Such minor apertures for the cores C30-C37 are respectively designated 166-173. Each of such minor apertures 166173 is included in a circuit responsive to the operation of control circuit 30 by divider 17 as described above for at times priming the minor apertures for causing an output to be provided on the readout winding of the minor aperture corresponding to the operating core.

Control circuit 30 may comprise, for example, a switching element such as a four-layer diode which may be operated from its blocked to its unblocked condition each time that control circuit 30 receives an input from divider 17 and a capacitor which is operated according to the condition of the four-layer diode. For example, the capacitor may be arranged such that it is charged during the interval that the four-layer diode is in a blocking condition through a circuit including the minor apertures 166- 173 of the interval timing register 25 and through a resistor 176 to energy. This charging circuit when effective also primes the minor apertures 166-173. Upon receiving an input from divider register 17, the four-layer diode is operated to an unblocked condition in which it permits the capacitor to be discharged through a circuit including the minor apertures 166-173 which discharging current fiow also drives the minor aperture corresponding to the operating core for providing a triggering output which is coupled through a coupling winding such as, for example, coupling winding 174 threading minor aperture 167 of core C31. to the corresponding interval driver. The four-layer diode when operated to an unblocked condition also supplies a reset signal to advance driver 29 for resetting the advance driver 29 to a condition wherein it is responsive to a received advance pulse supplied from AND gate 27 upon measurement of a time interval.

It has been described above that the divider 17 is operated to provide at its output ten pulses per second in response to the line frequency of 60 cycles per second as applied thereto through pulse shaper 15 and the driver 16. Prior to the occurrence of each pulsed output from divider 17, however, an output is provided to operate the control circuit 30 in the manner described supra for causing the operating core in the interval timing register 25 to provide an output to its corresponding interval driver. In other words, the operating core provides an output to its corresponding interval driver for each output of the divider 17 which is at the rate of ten pulses per second.

The interval driver circuit 23 includes interval drivers 1-8 corresponding respectively to the cores C30-C37 included with interval timing register 25. The successive pulsed outputs from an ope-rating core in the interval timing register 25 act as trigger pulses for the corresponding interval driver which operates to provide successive pulsed outputs. The successive pulsed outputs from an interval driver are applied to the contactor control register 32 as suggested in the block diagram of FIG. 1 and in FIG. 6.

One embodiment of an interval driver is shown in particular in FIG. 7 and this embodiment may be considered typical of the interval drivers 1-8. Referring now to FIG. 7, the interval driver includes a trigger input circuit including a transformer T2 through which pulsed trigger outputs from an operating core are applied. The interval driver includes a capacitor having a charging circuit including a coil 181, and a resistor 182. Minor apertures of the second time counters 10 and 11 corresponding to the selected positions of the interval time selector 22 are also included in the charging circuit for capacitor 180. The purpose of including such minor apertures of the cores in included time counters 10 and 11 is for the purpose of priming each minor aperture except the nonselected minor aperture prior to application of a drive input thereto which provides an output employed to ensure AND gate 27 remains in its OFF condition as suggested by the drawing of FIG. 5.

A discharge circuit for capacitor 180 includes a fourlayer diode 185, a diode 186, a coil 187 and a resistor 188. The discharge circuit of capacitor 180 also is coupled to contactor control register 32 and, more particularly, threads major and minor apertures of selected cores therein (see FIG. 8).

In operation, capacitor 180 is charged during the blocking state of the four-layer diode which time the minor apertures of all selected cores in time registers 10 and 11 are primed. Upon application of each trigger pulse through transformer T2, the breakover voltage of the four-layer diode 185 is exceeded which causes the four-layer diode 185 to conduct. Capacitor 180 'discharges through its discharge circuit including the fourlayer diode 185 until such time as the current flowing through the four-layer diode 185 is less than its holding current which causes the four-layer diode 185 to return to its blocking state.

The pulsed outputs supplied from the interval drivers 1-8 are applied over the buses 1-8 as shown in FIG. 6 and to the contactor control register 32 as shown more particularly in FIG. 8. Referring now to FIG. 8, it is seen that contactor control register 32 includes multiaperture cores C40-C45 each of which includes a major aperture and two minor apertures. One of the minor apertures for each of the cores C40-C45 is connected to one of tht buses 1-8 such as, for example, minor aperture 192 of core C42 being threaded by bus 1. The major apertures of the cores C40-C45 such as major aperture 194 of core C42 are included in a plurality of circuits extending from the buses 1-8 and in the direction of the arrows indicated in the drawing of FIG. 8.

The other minor apertures of the cores C40-C45 such as minor apertures 198 of core C42 are coupled to an RF generator 199 which continuously applies priming and reading pulses to such minor apertures. Each of the other minor apertures includes an output winding such as output winding 200 threading minor aperture 198 of core C42 coupled thereto which is further connected to signal control circuit 33.

In operation, the pulsed output from an operating interval driver corresponding to an operating core of the interval timing register 25 operates one or more of the cores C40-C45 according to the traffic and pedestrain signals desiring to be operated during the operation of one of the cores C30-C37 included with the interval timing register 25. For example, during the time that core C30 is operating, interval driver 1 is operated to supply pulsed energy over bus 1 for operating cores C40 and C42 to provide outputs to signal control circuit 33. In this connection, the outputs from respective cores C40- C45 may be employed to operate individual signal control circuits "including conventional relay circuits arranged to control the traflic and pedestrian signals through front and back contacts thereof.

FIG. 9 is a signal operation chart for indicating which of the traffic and pedestrian signals are operated during the different steps of the interval timing register wherein the multi-aperture cores C30-C37 are successively operated. For example, during the operation of core C30, its corresponding interval driver 1 of the interval driver circuit 23 is operated to provide a pulsed output over bus 1 which is coupled through minor aperture 192 of core C42 and minor aperture 201 of core C40 and the major apertures for all of the cores C40-C45. Cores C40 and C42 thus provide at their respective output

minor apertures

202 and 198 an output which is supplied over output windings 203 and 200 to respective signal control circuits. The output from core C40, for example, operates to control the green aspect display for the phase A signals SA and the red aspect display for the phase B signals SB. The output from core C42, for example, operates to control the WALK aspect display of the pedestrian signals SP1, while further controlling the WAIT aspect display of the pedestrian signals SP1, While further controlling the WAIT aspect display for the pedestrian signals SP2. It is suggested that operation of the cores C40C45 singly and in combination when any one of the buses 18 is being pulsed may be determined by following the forward direction of the arrow tips as indicated in FIG. 8. It is further suggested that the specific signals to be controlled thereby may be determined by referring to the signal operation chart of FIG. 9.

It has been suggested in connection with the block diagram of FIG. 1 that the gate and readout circuit 35 and particular ones of the interval drivers 18 upon receiving a phase A or phase B background signal operate to alter the predetermined timing relationship of the traffic and pedestrian signals in order to coordinate trafiic flow at two or more nearby intersections. The background signals may be provided over a communication channel and in the manner disclosed in the above mentioned Auer et al. application Serial No. 239,714.

Generally speaking, the application of a phase A or phase B background signal to the gate and readout circuit 35 functions to reset the

dividers

17 and 19 as well as the second time counters and 11 to initial operating conditions only at the time that the interval timing register is operating in the step wherein the corresponding green aspect display for that phase of traffic movement is operated.

Each of the cores C and C34 included in the interval timing register 25 includes an additional minor aperture, these being designated respectively 204 and 205. An RF generator 206 supplies priming and reading pulses continuously to these

minor apertures

204 and 205.

Output windings

208 and 209 coupled respectively to

minor apertures

204 and 205 couple respective outputs to the gate vand readout circuit 35 when the respective .12 core C30 or C34 is operating. It will be recalled that core C30 when operating corresponds to the phase A green aspect display traific signal, while core C34 corresponds to the phase B green aspect display traffic signal.

The gate and readout circuit 35 may include, for example, a transistor corresponding to each of the cores C30 and C34 which operates responsive to an output from its respective core to provide a reset output only in the presence of the corresponding phase A or phase B back ground signal. Such reset output is employed to return the

dividers

17 and 19 as well as the second time registers 10 and 11 to their initial operation conditions.

When employing the back ground signal type of operation, the energy for each of the

interval drivers

1 and 5 corresponding respectively to cores C30 and C34 of the interval timing register 25 is supplied through a switch, these switches being designated respectively 210 and 211. The application of (-1-) energy through either of these

switches

210 or 211 operates the respective interval driver in the manner suggested by the description of FIG. 7 provided that the corresponding core C30 or C34- is then operating. Prior to the termination of the energy background signal to the interval driver 1 or the interval driver 5, the corresponding phase A or phase B background signal is applied to the gate and readout circuit 35. The reset output is then derived from the circuit 35 which functions to reset the

dividers

17 and 19 as well as the second time counters 10 and 11. For example, and referring to FIG. 4, the reset output from circuit 35 is employed as a clear signal and is coupled through the minor apertures 63 of core C4 and the major apertures of cores C5C13 of the divider register for clearing each of the cores C5-C13 and setting core C4. The same clear output is coupled through the major apertures of cores C16C24 of the second time register shown in FIG. 5 for clearing such cores and through minor aperture 146 of core C15 for setting that core.

The individual time interval during which each of the cores C31C33 and C35C37 of the interval timing register 25 operates continues to be dependent upon the selections made by interval time selector 22 of the outputs of the second time registers 10 and 11 in the manner described above.

A typical interval time selector 22 is shown in FIG- URE 10. Thus, energization of any one of the eight output leads of the interval driver circuit 23 of FIGURE 6 is effective to energize one of ten input leads to the one second counter 10 and one of ten input leads to ten second counter 11. As each of the eight output leads of the interval driver circuit is energized in sequence, a different pair of leads to the counters 10 and 11 is energized. In this way, a different units and tens count of the counters 10 and 11 is associated with each step of the interval timing register 25 of FIGURE 6.

Having described a traflic signal controller of the pretimed type for highways as a specific embodiment of the present invention, it should be understood that the embodiment illustrated is considered as being merely typical and that various modifications and alterations may be made to the specific form shown without departing from the spirit or scope of this invention.

What I claim is:

1. In a controller for operating a traflic signal through its signal cycle at an intersection, the combination comprising,

(a) cycle demarcating means operable through a plurality of successively different conditions for demarcating the various portions of said signal cycle on each of which a trafiic signal is controlled to display a different combination of signal indications,

(b) counting means for measuring each of a plurality of difierent time intervals from a single starting condition to a particular one of a plurality of different operating conditions,

(c) control means responsive to said cycle demarcating means in each condition of its plurality of different conditions for controlling said traflic signal to display the corresponding combination of signal indications,

(d) means controlled by said cycle demarcating means for controlling said counting means to provide an output when it operates to the particular condition thereof corresponding to the measured time interval allotted to that condition of said cycle demarcating means,

(e) and means responsive to each output provided by said counting means for each of said plurality of different conditions in Which said cycle demarcating means operates to advance said demarcating means to its next condition and for returning said counting means to said single starting condition.

2. The controller according to claim 1 wherein said cycle demarcating means includes a plurality of electronic devices operable in sucession to each define one of the plurality of successively different conditions through which said cycle demarcating means is operated, said control means having a plurality of driver circuit means, one corresponding to each of said plurality of electronic devices and responsive to the operation of that electronic device for a time period corresponding to the measured time interval for controlling said traflic signal to display the combination of signal indications allotted to that portion of the signal cycle.

3. The controller according to claim 2 wherein said control means includes coupling means for connecting each of said plurality of driver circuit means to said counting means at the particular one of its plurality of different operating conditions which demarcates the measured time interval during which a corresponding one of the electronic devices of said cycle demarcating means operates, whereby said means is rendered responsive when said counting means is operated to the particular one of its different operating conditions which corresponds to the operating electronic means of said cycle demarcating means and its driver circuit means then operating.

4. The controller according to claim 3 wherein each of said plurality of electronic devices is a multi-aperture ferrite core having a major aperture and at least three minor apertures, each of two minor apertures for each core being coupled to one minor aperture of an adjacent core, and the third minor aperture for that core being coupled to its coresponding driver circuit means, said means having driving means effective when said means is rendered responsive for driving the operating core of said cycle demarcating means to cause transfer of operation between that core and an adjacent core through their coupled minor apertures for causing the adjacent core to provide an output at its third minor aperture, whereby the driver circuit means corresponding to said adjacent core is operated, said counting means being returned to its single starting condition from which it is operated to one of said plurality of different operating conditions for measuring the time interval allotted to the operating core of said cycle demarcating means.

5. The controller according to claim 1 wherein said counting means includes a plurality of electronic devices operable for measuring each of the plurality of diiferent time intervals and a pulsing means eifective to produce an output comprised of successive pulses for operating said plurality of electronic devices one at a time, each pulse being produced within a predetermined time period, a first one of the electronic devices when operating being edective to define said single starting condition of said counting means and other ones of said electronic devices being effective when operating to define particular ones of said plurality of diflerent operating conditions of said counting means, whereby each time interval measured by said counting means is comprised of a different given number of said predetermined time periods.

6. The controller according to claim 5 wherein said pulsing means includes a plurality of electronic devices operable in succession responsive to an applied power line energy having a predetermined frequency for providing an output signal at the output of the last-operated electronic device in the predetermined time period of the frequency, said counting means further including driving means responsive to each such output signal for operating a different one of the time measuring electronic devices, whereby each of said plurality of different time intervals is measured by the time measuring plurality of electronic devices means for the respective different conditions through which said cycle demarcating operates.

7. A controller for controlling the signal indications displayed by traffic signals at the intersection of conflicting rights of way comprising, in combination, a digital counter, a source of discrete pulses having a predetermined rate for driving said counter, a register having a predetermined number of steps and operable to each step in turn, signal control means responsive to said register for controlling said signals to display a distinctive combination of signal indications on each step of said register, means responsive to said register for setting said counter to count a predetermined number of said pulses according to the then-operated step of said register, and means responsive to the counting of said predetermined number of pulses for advancing said register to the next step and for resetting said counter.

8. The controller of claim 7 wherein said register includes a ring counter having at least one step for each different combination of signal indications displayed by said trafiic signals.

9. The controller of claim 8 in which said pulse source includes pulse generating means connected to a commercial alternating-current source having a predetermined frequency, said pulse generating means generating pulses at a rate which is a sub-multiple of said predetermined frequency.

References Cited by the Examiner UNITED STATES PATENTS 2,878,423 3/1959 Kips 340-41 3,090,032 5/1963 Shand 340 --40 3,175,193 3/1965 Willyard 34035 NEIL C. READ, Primary Examiner.

THOMAS B. HABECKER, Examiner.

Claims

1. IN A CONTROLLER FOR OPERATING A TRAFFIC SIGNAL THROUGH ITS SIGNAL CYCLE AT AN INTERSECTION, THE COMBINATION COMPRISING, (A) CYCLE DEMARCATING MEANS OPERABLE THROUGH A PLURALITY OF SUCCESSIVELY DIFFERENT CONDITIONS FOR DEMARCATING THE VARIOUS PORTIONS OF SAID SIGNAL CYCLE ON EACH OF WHICH A TRAFFIC SIGNAL IS CONTROLLED TO DISPLAY A DIFFERENT COMBINATION OF SIGNAL INDICATIONS, (B) COUNTING MEANS FOR MEASURING EACH OF A PLURALITY OF DIFFERENT TIME INTERVALS FROM A SINGLE STARTING CONDITION TO A PARTICULAR ONE OF A PLURALITY OF DIFFERENT OPERATING CONDITIONS, (C) CONTROL MEANS RESPONSIVE TO SAID CYCLE DEMARCATING MEANS IN EACH CONDITION OF ITS PLURALITY OF DIFFERENT CONDITIONS FOR CONTROLLING SAID TRAFFIC SIGNAL TO DISPLAY THE CORRESPONDING COMBINATION OF SIGNAL INDICATIONS, (D) MEANS CONTROLLED BY SAID CYCLE DEMARCATING MEANS FOR CONTROLLING SAID COUNTING MEANS TO PROVIDE AN OUTPUT WHEN IT OPERATES TO THE PARTICULAR CONDITION THEREOF CORRESPONDING TO THE MEASURED TIME INTERVAL ALLOTTED TO THAT CONDITION OF SAID CYCLE DEMARCATING MEANS, (E) AND MEANS RESPONSIVE TO EACH OUTPUT PROVIDED BY SAID COUNTING MEANS FOR EACH OF SAID PLURALITY OF DIFFERENT CONDITIONS IN WHICH SAID CYCLE DEMARCATING MEANS OPERATES TO ADVANCE SAID DEMARCATING MEANS TO ITS NEXT CONDITION AND FOR RETURNING SAID COUNTING MEANS TO SAID SINGLE STARTING CONDITION.