US3503041A - Traffic actuated control system - Google Patents

Description

March 24, 1970 c. L. Du VIVIER TRAFFIC ACTUATED CONTROL SYSTEM '7 Sheets-Sheet l Filed June 2, 1967 6511. VIE@ 2022 m m V m CHARLES L. DUV|V|ER ATTORNEY March 24, 1970 c. l.. Du VIVIER TRAFFIC ACTUATED CONTROL SYSTEM 7 Sheets-Sheet 2 Filed June 2. 196'? ATTORNEY March 24, 1970 c. l.. DU vlvu-:R

TRAFFIC ACTUATED CONTROL SYSTEM '7 Sheets-Sheet File-: June 2, 1967 March 24, 1970 Filed June 2, 1967 C. L. DU VIVIER TRAFFIC ACTUATED CONTROL SYSTEM 7 Sheets-Sheet 4 RED. RETURN z No CALL |543 CALL-AWAY oNE ADVANCE HOLD SHOT j SEMI-CALI.

A78 E MAXTIMER 1sT L! sEMl- CALL T z VEHICLE T|MER @'9| |38 J|92 (5) (l )tg ,|40 '4| 42 x lNTERvAL TIMES l l lM7 DC TR ST DMV (5) SEMI- CALL- 330 (2) N56 sToP T|M|NC lNTERvAL l -TIMER ADVANCE RESET HOLD Go To PREP.

sEM|CALL CALL-AWAY M64 i No CALL gAxTjMm EsET (2) i 23 FIG. 5 4 TR A ADVANCE 334 INVENTOR sEM|-CA| L. r CHARLES L. DuvlvlER sToP TIMING BY V @AMK/g ATTORNEY March 24, 1970 C, Du VIVIER 3,503,041

TRAFFIC AOTUATED CONTROL SYSTEM Filed June 2. 1967 '7 Sheets-Sheet 5 [|98 I94\ IMP (5) M coNv f204 l :GAP RESET 206 i208 f2|9 [220 STOP TIMING ST s' I 50 FF LVP I NO CALL `2I8 CALL AWAY L 205 2|7 HOLD IMP III `22| I GAP REDUCTION TIMER CONV FIG. 6

(232 234 236 I PASSAGE TIMER ST VEHICLE WAITING FIG. 7

Bx Ext HOLD 598 I al HOLD INVENTOR.

CHARLES L. DUVIVIER March 24, 1970 c. l.. DU vlvn-:R

TRAFFIC ACTUATED CONTROL SYSTEM Filed June 2. 1967 March 24, 1970 c. L. Du vlvlER 3,503,041

TRAFFIC AGTUATED CONTROL SYSTEM Filed June 2, 1967 '7 Sheets--Shee'cI '7 AIPNFFI BIPNFFI INVEN TOR.

A3 PNFFI Y CHARLES L DuvlvlER BBPNFFI `540 FSG. IO cwozffaw ATTORNEY United States Patent O U.S. Cl. 340--37 11 Claims ABSTRACT OF THE DISCLOSURE A solid-state traffic actuated multi-phase intersection right-of-way control system capable of providing right-ofway to up to two of a plurality of non-confiicting traffic phases selected from a larger plurality of trafiic phases at an intersection. Gating and control circuitry selects the traffic phases to which right-of-way is to be assigned, insuring that right-of-way is not simultaneously assigned to conliicting trafiic phases. Timing and counter circuitry steps each right-of-way period through its appropriate intervals. The right-of-way assignment can be changed from first and second non-confiicting traffic phases to third and fourth non-conflicting traffic phases, and one of the third and fourth phases may be the same as one of the first and second phases.

BACKGROUND OF THE INVENTION This invention relates to a traffic actuated multiphase trafiic intersection right-of-way control system. More particularly this invention relates to such a traic intersection right-of-way control system including all solid state circuitry in modular components and having the ability to assign right-of-way to one or more non-conflicting phases of a plurality of traf-lic phases at in intersection in accordance with the demand on any one phase relative to the overall demand on all trafiic phases.

While many trafiic intersections are primarily utilized by trafiic flowing straight through on one thoroughfare or straight through on the other intersecting thoroughfare, numerous intersections handle large quantities of traffic desiring to turn left from one thoroughfare, across the traffic lanes assigned for traic fiow in the opposite direction on that first thoroughfare, and into the second thoroughfare. So long as this left-turn trafiic is of a small volume it presents no great problem. However, when the volume of left-turn traffic increases appreciably, it becomes desirable to assign portions of the right-of-way period exclusively for the left-turn trafiic. For example, at an intersection of a north-south street and an east-west sreet, some trafiic traveling in a northerly direction may desire to turn left onto the east-west street to then travel in a westerly direction. To best accommodate large volurnes of this left turn traffic it is necessary to end the rightof-way period of the south-bound trafiic so that the leftturn traffic may pass in front of it.

If there is south-bound trafiic desiring to turn left into the east-bound lane, then, these two left-turn flows can take place simultaneously. This necessitates stopping the straight through north-bound tratiic. lf, however, there is no left-turn trafiic in the south-bound lanes, then the north-bound left-turn traffic can proceed simultaneously with the north-bound straight through traffic. Thus, the north-bound left-turn trafiic can proceed simultaneously either with the south-bound left-turn trafiic or with the north-bound straight through trafiic. Similarly, the southbound left-turn trafiic can proceed simultaneously either with the north-bound left-turn traffic or the south-bound straight through trafiic, and the north-bound straight through traffic and south-bound straight through trafiic 3,503,041 Patented Mar. 24, 1970 ice each can proceed simultaneously with their corresponding left-turn traffic or simultaneously with each other. Left-turn east-bound and west-bound trafiic similarly each have two trafiic fiows with which they can proceed. Thus, it is seen that at such an intersection any one trafiic fiow can safely take place at the same time as either one of two selected other traf-'ric fiows. Optimum assignment of right-of-way between the conflicting phases of the traic flow requires that any one phase be permitted to operate simultaneously with either one of its non-conflicting phases which has a demand for right-of-way.

Traffic control systems are available for providing right-of-way to each of two mutually confficting trafiic phases at an intersection. Use of such a control system at an intersection having large amounts of conflicting straight through and left-turn traffic results in the left-turn traffic encountering a great deal of difficulty. Not only does this result in only a few left-turn vehicles passing during each cycle of the control system, but also it presents a hazard because more vehicles attempt to turn left than can, with a resulting conflict between these left-turn vehicles and vehicles attempting to travel straight through on the subsequent phase. Left-turn traffic at a two-street intersection can be accommodated by use of a three-phase or a fourphase trafiic controller. Then, one phase is assigned exclusively for left-turn traffic in a three-phase controller or two phases of a four-phase controller are assigned for the two left-turn movements, i.e. one left-turn movement by the north-south traffic and another left-turn movement by the east and west bound traffic. The controller then cycles through its phases to periodically allocate right-ofway to this left-turn traffic. While this smoothes the traffic flow somewhat, it does not make optimum utilization of trafiic control equipment and it needlessly holds up one direction of straight through traffic when there is no trafiic turning left across its pathway until the left-turn traffic originating from the same direction as that straight through traic has terminated. Thus, optimum trafiic handling is not obtained.

Leftturn trafiic can also be accommodated by adding to a control system one or more small control units, frequently referred to as minor movement controllers, which interrupt the normal trafiic signal cycle sequence to provide left-turn indications prior to the straight through indications. By use of one such minor movement controller for each direction of left-turn trafiic, improved traffic flow can be obtained. However, the leftturn indication can only be provided at one selected point in the trafiic controller cycle. Thus, if at the time that point is reached there is no demand for the left-turn indication, then the left-turn is omitted, and the straight through indications are provided. If, shortly after the initiation of a straight through indication a demand for a left turn originates on that phase, that demand must remain unsatisfied until the selected point in the cycle is again reached. If there is no demand on the intersecting roadway, either right-of-way must still be transferred to that roadway in order to cycle through to the point at which the minor movement controller can allow left-turn traffic to have the right-of-way, or further control equipment must be added to enable the system to skip the phase having no demand. Thus, obtaining optimum trafiic control with such a system requires numerous complex ieces of control equipment, thereby increasing the likelihood of an equipment malfunction.

Trafiic control systems have been developed which are of unitary design and which are able to improve trafiic flow by omitting one or more phases of a traffic controller cycle in order to provide a left-turn indication when demanded on a street which has right-of-way, in the absence of a call for the traffic right-of-way from a conflicting phase. These traffic control systems heretofore have been large units utilizing vacuum tubes, relays, cams, and other electro-mechanical devices Not only do such systems consume large amounts of power, they also are subject to frequent breakdown due to the nature lof the electro-mechanical devices.

In addition, prior art traffic control systems of this type have been incapable of adequately handling traffic approaching the intersection in waves or platoons. Consider, for example, an intersection of two streets, at least one of which has a high volume of left-turn traliic for which a separate tratiic phase is assigned. Each rightof-way period comprises several intervals. There will be an initial green interval, which may coincide with pedestrian walk and pedestrian clearance intervals if these are provided. Then there isa vehicle or passage interval during which right-of-way is continued on that traffic phase so long as the traffic volume on that phase justifies. This is followed by a brief interval, frequently known as a preparatory interval, during which the control system determines the phase to which right-of-way is to be transfered next. Then comes the yellow or clearance interval and perhaps an all-red interval for the traffic phase, following which right-of-way is transferred to another phase. If right-of-way at an intersection is assigned to a straight through traliic phase, for example east-bound straight through, and to the non-conflicting left-turn traic phase (i.e. east-bound left-turn becoming northbound) when a call for right-of-way is received from the opposite non-conicting straight through phase, (i.e., west-bound straight-through) followed by a call for rightof-way from a conflicting traic phase, for example, northbound, prior art traic control systems of this type have permitted the east-bound straight through phase circuitry to advance to its preparatory interval regardless of the status of the west-bound straight through right-of-way period, provided the straight-through traffic on the eastbound phase at some time reaches a low volume. But right-of-way is not transferred to the coniiicting northbound phase until the west-bound straight-through phase has passed through its vehicle interval to its preparatory interval. During the time the west-bound phase is in its initial interval, the east-bound trahie volume may increase considerably due to the arrival of another wave or platoon of traflic at the itnersection. However, in prior art traitic control systems of this type, the east-bound phase circuitry is held in its preparatory condition. Thus, if the West-bound traflic volume drops, right-of-way transfers to the conicting north-bound phase, cutting olf the east-bound platoon which is at the intersection. As a consequence, optimum trathc iiow is not achieved.

SUMMARY OF THE INVENTION The present invention is a trahie-actuated multi-phase traic intersection right-of-way control system in which during the time right-of-way is assigned to one traic phase, right-of-way can also be assigned to any one of a plurality of non-conicting traic phases selected from a larger plurality of traic phases at the intersection. The control system can change the right-of-way assignment from one of the non-conicting traflic phases to another non-coniiicting phase, while retaining right-of-way on the second non-conflicting traflic phase, as traflic demands require and in the absence of a call for right-of-Way on the conflicting traffic phases. In the event that right-of-way is given to a straight through traflic phase simultaneously with its non-conflicting left-turn traffic phase, and a call comes in for the non-coniiicting straight through right-ofway followed by a call for right-of-way on a conicting tratic phase, the first straight through traffic right-of-way is maintained in its vehicle interval at least until the rightof-way period has been assigned to the other straight through traic and has reached its vehicle interval. Thus, a platoon of traiiic arriving on the rst straight through phase while the seven@ straight through phase is in its initial interval is optimally handled. The traffic control system is made up entirely of solid state circuitry, with no vacuum tubes or moving parts, and it is adapted for simpliiied modulator construction, thus permitting easy expansion of the system to meet the growing requirements of an intersection.

It is accordingly an object of the present invention to provide an improved traic actuated multi-phase trallic intersection right-of-way control system.

It is another object of the present invention to provide an improved trahie-actuated multi-phase intersection controller having a simplied solid state design resulting in improved performance and reliability.

It is a further object of the present invention to provide a traffic controller which permits optimum assignment of right-of-way at intersections having complex traliic requirements.

It is yet another object of the present invention to provide a traiiic intersection right-of-way controller which, during the time that right-of-way is available to any one traic phase, can assign right-of-way simultaneously to any one of a plurality of non-conflicting traffic phases and which in response to a demand therefor can change that assignment to lany other non-conicting trafc phase in the absence of a call for right-of-way from a conflicting traffic phase.

It is a still further object of the present invention to provide a traffic intersection right-of-way control system capable of simultaneously allocating right-of-way periods, each having a plurality of intervals, to first and second non-contlicting traffic phases at an intersection and, when a call for right-of-way is received from a third trahie phase conflicting with the second phase but not with the rst, capable of holding the right-of-way period of the lirst phase in au intermediate interval from which it can not be removed in the presence of continuing traic demand even in the presence of a call for right-of-way from a fourth phase, conflicting with the first three phases, where the fourth phase call arrives after the third phase call, the irst phase right-of-way being held in that intermediate interval at least until the third phase has received right-ofway and has reached the corresponding intermediate interval.

These and other objects and advantages of the present invention will be apparent from the following detailed description and claims, particularly when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a street intersection at which the right-of-way is controlled -by the traflic actuated multiphase control system of the present invention.

FlG. 2 is a block diagram of the traffic actuated multiphase traflic control system of the present invention.

FIG. 3 is a detailed block diagram of the counter circuitry within the interval sequence units used in the present invention.

FIG. 4 is a detailed block diagram of a phase control unit for use in the present invention in connection with any of the traic phases.

FIG. 5 is a detailed block diagram of the gating and timing circuitry within an interval sequence unit as used in the present invention.

FIG. 6 is a detailed block diagram of gap timing circuitry within the interval sequence units used in the present invention.

FIG. 7 is a detailed block diagram of a passage timing circuit within the interval sequence units used in the present invention.

YFIG. 8 is a block diagram of the phase sequence unit of the present invention showing in detailed block form the portion of the phase sequence unit which works in common with all traliic phases at the intersection.

FIG, 9 is a block diagram depicting one Strt of phase selection circuitry within the phase sequence unit used in the present invention.

FIG. is a detailed block diagram of the transfer gating circuitry within the phase sequence unit used in the present invention.

FIG. 11 is a detailed block diagram of a set of hold gating circuitry utilized to coordinate operation of the system and found within the phase sequence unit used in the present invention.

DESCRIPTION OF A PREFERRED EMBODIMENT FIG. l depicts a street intersection which may be controlled by means of a multi-phase trafiic actuated intersection control system incorporating the present invention. The intersection depicted in FIG. 1 includes two streets, each having two lanes of travel in each of two directions, the two lanes of travel being divided by a median or divider strip. There is provided in each direction of travel for a brief distance approaching the intersection an additional lane for the convenience of vehicles desiring to make a left turn into the cross street. The east-West street is designated street I, while the north-south street is designated street II. There are thus eight phases of tratiic approaching the intersection: phase A1, the straight through west-bound traic; phase A2, the straight through eastbound traic; phase A3, the straight through south-bound traiiic; and phase A4, the straight through north-bound traic; phase B1, the east-bound left-turn traic becoming north-bound; phase B2, the west-bound left-turn traffic `becoming south-bound; phase B3, the north-bound leftturn tral'lic becoming west-bound; and phase B4, the south-bound left-turn traic becoming east-bound. These designations are of course only for convenience and are in no way limiting. By means of these designations it is seen that each straight through traic phase is designated as an A phase while each left-tum tratlic phase is designated as a B phase. In addition, it can be seen from FIG.

1 that each odd traic phase conilicts with all other odd traflic phases and that each even traic phase conicts with all other even traic phases. In addition, there are conicts between certain odd-even pairs of traflic phases such as phases B1 and B4, phases B1 and A4, and phases A2 and A3, for example. The pairs of non-conflicting traic phases which can operate simultaneously at the illustrative intersection depicted in FIG. 1 are thus the following: phases A1 and A2, phases -A1 and B2, phases A3 and A4, phases A3 and B4, phases B1 and A2, phases B1 and B2, phases B3 and A4, and phases B3 and B4. Each of these pairs is seen to include one odd phase and one even phase due to the designations used in this illustrative example.

Vehicles on each traicphase approaching the intersection are monitored by a vehicle detector, depicted in FIG. 1 by the vehicle detector blocks D shown in the roadway approaching the intersection for each traic phase. Thus, for example, vehicles on phase A1 are monitored by detector DA1, vehicles on phase B3 are monitored by vehicle detector DB3, etc. Each of these vehicle detectors may be any one of a number of types. For example, each m-ay be an overhead detector of a radar or sonic type. Alternatively each may be imbedded in the roadway, in which case they may be inductive loop, magnetic, or treadle detectors, for example. It is required only that each detector generate an electrical signal upon the passage of a vehicle in its detection zone, although a detector providing an electrical signal in response to the presence of a vehicle may be used, if desired.

Manually actuated push-buttons are provided at the corners of the intersection, to be actuated by pedestrians desiring to cross the intersection. These pedestrian pushbuttons are shown in each corner of the intersection by the outlines P, and they are designated in accordance with the vehicle phase with which they cooperate. Thus, a pushbutton PA1 is utilized by pedestrians wishing to cross the intersection in -a direction parallel with vehicle phase A1, etc. Pedestrians desiring to cross the intersection push the appropriate pedestrian button to actuate circuitry in the invention which results in signalling of a pedestrian rightof-way interval.

Tralic control signals to control right-of-way phases for each traic ph-ase and for each pedestrian phase are provided at the intersection. For clarity these traffic control signals are collectively depicted in FIG. l by the circle S at the center of the intersection; however, they might conveniently be located directly in front of the traffic lanes corresponding to each phase and directly facing pedestrians desiring to cross the intersection.

Each of the vehicle detectors D and pedestrian pushbuttons P and the traffic control signal S is connected by means of cabling (not shown) to a terminal box TB illustratively shown in one corner of the intersection. Such a terminal box housing the necessary circuitry for the present invention might be placed lat any convenient location at or near the intersection or might be placed at a remote location.

FIG. 2 depicts the multi-phase traic actuated intersection control system of the present invention in block diagram form. A phase control unit is associated with each tralc phase at the intersection. Thus, phase control unit 10 is associated with the traic phase A1, phase control unit I12 is associated with traffic phase A3, phase control unit 14 is associated with traffic phase B1, phase control nnit 16 is associated with tr'aic phase B3, phase control unit 18 is associated with traiilc phase A2, phase control unit 20 is associated with traflic phase A4, phase control unit 22 is associated with traic phase B2, and phase control unit 24 is associated with traic phase B4.

Each phase control unit receives indications from its associated vehicle detector and pedestrian push-buttons and transmits signals to the associated vehicle and pedestrian signal lights. Phase control unit 10 associated with traflic phase A1 is typical of the phase control units which are associated with the four phase A traic phases. Phase control unit 10 receives vehicle detection signals from the vehicle detector DA1 and receives pedestrian call signals from the pedestrian push-buttons PA1. Phase control unit 10 provides appropriate outputs for control of the vehicle and pedestrian signal lights of phase A1 for control of right-of-way and clearance. Each of the other phase A control units 12 for A3, 18 for A2, and 20 for A4 is similar to phase control unit 10, but has inputs from the vehicle detector and pedestrian pushbutton of the associated phase and has outputs for the traffic control signals for such phase.

Phase control unit 14, assoicated with traic phase B1, is typical of the phase lcontrol units which are associated with the four -B traffic phases. Control unit '14 receives v vehicle detection indications from vehicle detector DB1 and provides control outputs to vehicle traflic signals associated with phase B1. Phase control units 16, 22, and 24 associated respectively with traflic phases B3, B2, and B4 similarly receive vehicle indications from the vehicle detectors DB3, DB2, and DB4 associated with their respective traffic phases and provide vehicle control signals to the associated traic signals. Since the B traic phases are left-turn phases at the intersection of FIG. 1, no pedestrian actuations or pedestrian control signals are associated with the phase control units at phase B.

Each of the phase control units 10, 12, 14, 16, associated with the odd traiiic phases, is connected to interval sequence unit 26 which determines the sequence of intervals for the control periods of the odd traffic phases. These odd phase control units both receive signals from interval sequence unit 26 and apply signals to interval sequence unit 26. Similarly, each of the phase control units 18, 20, 22, 24, is connected to interval sequence unit 28 which determines the sequence of intervals for the control periods of the even traliic phases. Each even phase control unit 18, 20, 22, 24 both receives signals from interval sequence unit 28 and applies signals to interval sequence unit 28.

Each of the phase control units 1024 and each of the interval sequence units 26 'and 28 is connected to phase sequence unit 30 to both receive signals therefrom and apply signals thereto. Phase sequence unit 30 determines which phase control units shall provide right-of-way indications at any one time and which phase control units shall be next to supply right-of-way indications, insuring that no conflicting right-of-way indications are provided. At any one time one of the odd phase control units 10, 1.2, 14, 16 may be selected by phase sequence unit 30 to provide control indications to its associated trathc phase and a non-conflicting one of the phase control units 18, 20, 21, 24 may be simultaneously selected to provide control indications to its associated traffic phase.

The phase control units selected by phase sequence unit 30 from the phase control units 10424 provide ap propriate control indications for their associated trafc phases and develop voltage analogs of the durations of each interval of the control sequence. Interval sequence unit 26 monitors these analog timing signals for the selected odd traliie phase, and in response to these monitored signals, the interval sequence unit 26 provides indications for a sequence of steps and appropriate intervals for the control period of that selected odd phase control unit. Similarly, interval sequence unit 28 monitors the analog timing signals for the selected even trafc phase control unit and provides indications for a sequence of steps and a-ppropriate intervals for the control period for that selected even phase.

INTERVAL COUNTER-FIGURE 3 FIG. 3 depicts a nine position counter, one of which is used in each interval sequence unit. The counter cornprises two three- position units 52 and 54. Each of these units comprises a trinary counter, and the two units are connected to obtain nine discrete count positions. A trinary counter suitable for this use is disclosed in U.S. Patent No. 3,267,424 granted to Peter C. Brockett and Charles L. DuVivier on Aug. 16, 1966, particularly in conjunction with components 356 and 356 in FIGURE 5 of that of that patent. The outputs of the three stages of each of the counter units 52 and 54 are coupled to AND gates 56-72 in such a manner that the outputs of the gates 56-72 correspond respectively with the positions 1-9 of the counter output. Pulses applied to the stepping input of counter unit 52 via line 74 sequentially step the counter through its nine positions. Thus, if the counter is in its position 1 so that signals are applied to the two inputs of AND gate 56, then gate 56 provides an output signal. Application of a pulse on line 74 steps the counter to its position 2, resulting in termination of the signal applied from counter unit S2 to AND gate S6 and application of signals to the two inputs of AND gate 58. Thus, the position 1 output from gate 56 ends and a position 2 output signal is provided from gate 58. The next pulse on line 74 steps the counter to its position 3, thereby terminating the output from gate 58 and initiating an input from AND gate 60. Under some conditions the advance pulse is blocked from line 74 and instead sets the counter to another position which skips one or more intermediate positions, as explainedl more fully hereinafter. When the counter is in its position 9, a pulse on line 74 returns it to position 1, returning the position 1 output signal from gate 56.

The counter position outputs 1-9 obtained from gates 56-72 respectively as the nine position counter moves through its positions correspond to intervals in the control period. Thus the rst counter position, in which an output is obtained from gate 56, corresponds to the first interval of the control period known as the green skip interval. This is a short duration interval providing a green or go indication to vehicular traic while maintaining a. dont walk or wait indication for pedestrians. Should it be desired to provide sub-cycles by use of auxiliary control equipment, these sub-cycles can be operated while the counter is in its position 1. If necessary, the green indication can be inhibited during such a sub-cycle.

The second position of the counter, during which an output is obtained from gate 58, corresponds to the pedestrian interval of the control period. During this interval a green indication is provided for vehicular traic and a walk indication is provided for pedestrian traic. During the third counter position an output is provided from gate 60 to cause a green indication for vehicular traliic and a clearance interval for pedestrians, during which the pedestrian indicators may provide a flashing dont walk or a flashing wait indication, for example.

In position 4 of the counter an output is generated by gate 62. During this condition a green indication is provided for vehicular traiilc and a wait indication for pedestrians. This counter position corresponds to the initial interval of the control period during which the intersection may be entered -by vehicles which had approached the intersection during the red indication and which were between the vehicle detector and the intersection waiting for right-of-way. Position 5 of the counter corresponds to the vehicle interval of the control period. In this position an output is obtained from gaate 64, and a green indication is provided to vehicular traffic While a wait indication is provided to pedestrians. The sixth position of the counter is a preparatory interval during which phase sequence unit 30 determines which phases of the intersection are to have right-ofway next, as will be more fully described hereinafter. During this preparatory interval a signal is obtained from gate 66 to cause a green indication for vehicular traiiic and a wait indication for pedestrians.

In position 7 of the counter an indication is provided from gate 68 to cause a yellow or clearance indication for vehicular traffic and wait indication for pedestrians. This is the vehicle clearance interval. The eighth counter position corresponds to the all red interval of the control period during which a red indication is provided to all vehicular traffic and a wait indication to all pedestrians. In this position an output is provided from gate 70. The ninth counter position is a transfer position during which a signal is provided from gate 72. In this position all the vehicular indicators provide a red indication and the pedestrian signals provide wait indications. During this transfer interval, transfer is made from the phase timing unit which has just completed its control period to the phase timing unit to which the next control period is assigned.

The output of the last stage of counter unit 54 is connected to the input of inverter 76 so that during counter positions 7, 8, and 9 a signal is applied to the input of inverter 76. Thus, when the counter is in any one of its positions 1-6, no input is applied to inverter 76, and so the inverter supplies an output signal. During these counter positions 1-6 the vehicular traiiic is provided a green indication. Thus, any time this green indication is to be provided to the vehicular traic, inverter 76 supplies a signal, referred to as the E Green signal.

When the traffic control system is iirst placed into operation, a start signal is applied via line 77 to counter units 52 and 54 to set the counter to its 7 position. This causes a signal from gate 68 to energize the yellow indication for vehicular traiiic. Subsequent advance pulses applied on line 74 step the counter through its positions 8 and 9 in which the control period is transferred to another phase under the control of phase sequence unit 30. The counter then returns to position 1, the green skip posi tion. If there has been a pedestrian call on the phase to which r-ight-o-way has now been transferred, a signal passes through OR gate 78 to block INHIBITED-AND gate 79. The next advance pulse on line `89 passes through gate 80 to step the counter to its position 2 to provide a green indication for vehicles and a walk indication for pedestrians. At the conclusion of the pedestrian interval, an advance pulse on lines 89 and 74 steps the counter to position 3 to provide the pedestrian clearance interval. In this position a signal from gate 60 is applied to one input of AND gate 81 and via OR gate 90 to the inhibit input of INHIBITED-AND gate 80. As a consequence the next advance pulse on line 89 is blocked from line 74, and instead it passes through gate 81 and through OR gates 82 and 84 to set the counter to position 5. Thus, when a pedestrian call has resulted in the counter cycling through the pedestrian and pedestrian clearance intervals of counter positions 2 and 3, the initial interval of position 4 of the counter period is omitted, and the pedestrian and pedestrian clearance intervals replace it. The controller moves immediately to the vehicle interval of counter position 5 after the pedestrian clearance interval has terminated.

Position 5 is a rest position for the counter, and so it remains in this position until a command to step to another position is received. During counter position 5, the signal from AND gate 64 passes to one signal input of INHIBITED-AND gate 86. If there are no calls for rightof-way from a conflicting traiiic phase assigned to the same interval sequence unit, the E no call signal is also applied to a signal input of gate 86. If no call for right-ofway is present on a conflicting phase assigned to the other phase sequence unit, the signal call away is not present at the inhibit input of gate 86. Should a pedestrian call then be received on the phase which has right-of-way, a signal passes through OR gate 78 to the third signal input of gate `86. Gate 86 then applies a signal through OR gate 90 to block gate 80. This same signal from gate 86 is applied to the first input of AND gate 92. Via line 88 this condition also transmits the signal pedestrian return to the gating and timing circuitry of FIG. 5 to cause an ad- Vance pulse on line 89, as described more fully hereinafter. This advance pulse is blocked at gate 80 and passes through gate 92 to return the counter to its position 2, thus providing a walk indication in response to that pedestrian call. Hence, the control system is capable of returning from its rest position in the vehicle interval to provide pedestrian right-of-way in the event of a pedestrian call on the phase which has right-of-way when no conflicting calls have been received.

If there has been no pedestrian call when the counter is in the green skip interval at position 1, then during the time that the counter is in position 1, the position 1 signal is applied from the output of INHIBITED-AND gate 79 through OR gate 90 to block gate 80. This signal from gate 79 is also applied to the iirst input of AND gate 96. The next advance pulse therefore, passes through gate 96 and through OR gates 84 and 98 to set the counter to position 4, providing a green vehicular indication and a wait pedestrian indication. This is the initial interval of the rightof-way period, and so in the absence of a pedestrian call, the pedestrian walk indication is omitted. Instead, the control System steps from counter position 1 to the vehicle initial interval in counter position 4, at the conclusion of which an advance pulse steps the counter position 5, the vehicle interval of the right-of-way period, where it rests. Hereinafter where it is stated that the counter steps to a position, it is meant that the counter moves to that position in response to an advance pulse.

If the control system is next to provide right-of-way for a phase conicting with that on which right-of-way is presently provided, the counter next moves to position 6 either in response to an advance pulse or in response to the go to prep signal, as explained hereinafter. Position 6 is the green preparatory position during which position the phase sequence unit 30 determines the phase control unit or units to which control is next to be assigned. At the termination of the green preparatory position, the counter steps to position 7 to provide the vehicle clearance interval on the phase from which right-of-way is being 10 transferred. At the conclusion of the clearance interval, the counter provides a brief all-red interval in its position 8. In position 9 the actual phase transfer takes place, following which the counter steps to position 1 to provide control to the newly assigned phase.

In counter position 3, the pedestrian clearance interval, power is applied to free-running multivibrator which then provides a flashing power for causing the pedestrian clearance indicator to ilash in the event no ilashing power is available within the indicator itself.

PHASE CONTROL UNITS-FIG 4; GATING AND TIMING CIRCUITS-FIG. 5

FIG. 4 depicts in detail block diagram form the circuitry of each phase control unit 10i-24. Each phase control unit is associated with one traic phase at the intersection and so receives input signals from a vehicle detector, such as vehicle detector DA1, associated with trafic phase A1. This vehicle detector, shown in FIG. 4 as vehicle detector 102, applies -ground to the input of inverting amplifier 104 each time a vehicle passes through its detection zone. The resulting positive pulse from ampliiier 104 passes through OR gate 106 to trigger locking delay multivibrator 108. Locking delay multivibrator 108 is a monostable multivibrator including a gate to provide memory when a locking input is applied. Thus, with no locking input, a trigger input causes the multivibrator to assume its unstable state for a period of time determined by the time-constant of the multivibrator circuitry, just as in a one-shot multivibrator. With a locking input L, the multivibrator remains in its stable state until a trigger input is applied to it, at which time it assumes its` unstable state and remains there until the locking input terminates. Following termination of the locking input, the multivibrator remains in its unstable state for a period of time determined by the time constant of its circuitry, after which it returns to its stable state. This locking multivibrator is hereinafter called DMV 108. A circuit suitable for this use is disclosed in FIG. 8 of U.S. patent application Ser. No. 586,881 tiled Oct. 14, 1966 by Charles L. Du Vivier and Peter C. Brockett and assigned to the same assignee as the present application.

Each time a vehicle passes through the detection zone of vehicle detector 102, the one output of DMV 108 applies a pulse through OR gate 110, INHIBITED-AND gate 112, and OR gate 114 to set phase memory flip-flop (PMFF) 116 to its one condition. When the system is rst placed into operation the start signal passes through OR gate 106 to have the same effect as a vehicle detection pulse. The one output fromy Kflip-liep PMFF 116l is applied through OR gate 117 to generate the output signal PMFFI, indicating that there has been a call for right-of-way on the traic phase associated with this phase control unit. This output is applied to phase sequence unit 30. When no call has been received for this phase PMFF 116 is in its zero condition, and the signal PMFFO is applied to AND gate 117 which provides the no call signal to the interval sequence unit of FIG. 5 where it s summed with the no call signals from other phases.

When the tratiic phase associated with this phase control unit is to be the next traic phase to have right-ofway, as determined by phase sequence unit 30, the signal PNFFSI is applied to the set one input of phase next ip-ilop (PNFF) 118. As a consequence PNFF 118 provides its one output signal PNFFI as an input to AND gate 119. When the counter within the associated interval sequence unit reaches its position 1 at the start of its next control cycle, a signal is applied to the other input of gate 119. Consequently, a signal passes from gate 119 to the set one input of phase flip-flop (PFP) 120. This switches PFP 120 from its zero condition, in which it provides the output PFFI), to its one condition in which it provides the output PFFI. During counter positions 2 and 4 signals pass through OR gate 118 to reset PNFF 118 to its zero condition. During counter position 9 the l l output of lgate 72 is applied to the set zero input of PFF 120 to return the flip-flop to its zero condition. The PFP 1 output of PFF 120 is applied to one input of AND gate 120.

Counter positions 2, 3, 4, 7 and 8 pertain to intervals of the control sequence having fixed time durations for any one tratlic phase. Within each phase control unit variable resistor 121 has one end connected to an input terminal to which a signal is applied from AND gate 58 when the counter of FIG. 3 is in its position 2. Similarly within each phase control unit a signal from gate 60 is applied to one end of variable resistor 122 during counter position 3; a signal from gate 62 is applied to one end of variable resistor 123 during counter position 4; a signal from gate 68 is applied to one end of variable resistor 124 during counter position 7; and a signal from gate 7G is applied to one end of variable resistor 125 during counter position 8. The second end of each of the variable resistors 121-125 comprise the inputs to OR gate 126 which has its output connected to the first plate of capacitor 127. The second plate of capacitor 127 is tied to ground.

When this phase control unit is not controlling rightof-way, the signal PFFtl from PFF 120 passes sequentially through - OR gates 128 and 130` to the input of gating amplifier 132. When a signal is applied to the input of gating amplifier 132, the amplifier Output is substantially -ground potential, clamping capacitor 127 to that potential. With no input to gating amplifier 132, its output line is open circuited, permitting voltage to build up on capacitor 127 due to current through one of the resistors 121-125.

When this phase control unit is controlling the intersection, signal PFFG is not present, and so capacitor 127 is not clamped to ground. Then, during counter position 2, resistor 121 and capacitor 127 form a circuit which develops a voltage analog of the time duration of the pedestrian interval of the control sequence. Similarly, in counter positions 3, 4, 7, and 8, the corresponding resistors 122-125 together with capacitor 127 develop voltage analogs of the time durations of the corresponding intervals of the control period.

The output of this interval timing circuit is obtained from the first plate of capacitor 12-7 through diode 134 to output terminal 136 which ties it to terminal 138 Within the gating and timing circuitry of the associated interval sequence unit, as shown in FIG. 5. From terminal 138 the signal passes through OR gate 140 and I-NHIBITED- AND gate 141 to Schmitt trigger 142. Since the firing level of Schmitt trigger 142 is fixed, the time durations of the various intervals of the control period are determined by the length of time required for the voltage analog on capacitor 127 to reach this firing level. That length of time is determined by the adjustment of the corresponding variable resistor 121-125. OR gate 140 also receives an input during counter position 1 to fire Schmitt trigger 142 during the green skip interval. The output of Schmitt trigger 142 is tied to the input of direct coupled monostable multivibrator 144 (hereinafter referred as direct coupled delay multivibrator or DC DMV). Since the input to the DC DMV is direct coupled, its output signal is present so long as the input signal is applied. Upon termination of the input signal, the DC DMV output continues for a fixed length of time, similar to the operation of AC coupled one-shot multivibrator upon application of a triggering pulse. The output from DC DMV 144 passes through OR gate 148, INHIBITED- AND gate 150, and OR gate 152 to trigger monostable multivibrator or one-shot 154. The output of one-shot 154 is the advance pulse on line 89 which causes counter units 52 and 54 to step through their counting cycle. Thus, it is seen that during those intervals of the control sequence which have fixed time durations, the timing circuit comprising one of the resistors 121-125, capacitor 127 and Schmitt trigger 142, operates with DC DMV 144 and one-shot 154, to provide the proper time duration for that interval before generating the advance pulse.

OR gate 152 also receives an input on line 88 from gate 86 Within the counter circuitry of FIG. 3 when a pedestrian call has been received on the phase which is resting in its vehicle interval in the absence of a call from a conflicting phase. This input causes the advance pulse which returns the counter to its position 2 to provide a walk signal.

Within the timing circuitry of FIG. 5, the advance pulse obtained from one-shot 154 is applied through OR gate 156, the output of which is the interval timer reset signal that is transmitted to each phase control unit. Within the phase control unit of FIG. 4 this interval timer reset signal passes through OR gate to the input of gating amplifier 132, discharging capacitor 127 to ground.

So long as there is no call from a phase conflicting with that phase which has right-of-Way, then the signal 2 no call passes through vINI-IIBITED-AND gate 162 in the interval sequence unit gating and timing circuitry of FIG. 5. This signal then passes through OR gate 164, the output of which is the maximum timer reset signal which is applied to each phase timing unit. The signals for counter positions 2, 3, and 4 pass through O-R gate 166 in FlG. S to the inhibit input of INHIBlTED-AND gate 168, which has the advance pulse applied to its signal input. Thus, during the counter positions 2, 3, and 4 the advance pulse is blocked from passage through gate 168. The output of gate 168 is tied to the input of OR gate 164 from which the maximum timer reset signal is obtained.

As shown in FIG. 4, each phase control unit includes a maximum timer, comprising capacitor 170 and variable resistor 172 tied together between a source of positive voltage and ground. When another phase control unit is controlling the intersection, the signal PFFG passes sequentially Vthrough OR gates 128 and 174 to gating amplifier 176 which clamps capacitor 170 to ground, operating in the same manner as amplifier 132. Similarly, the maximum timer reset signal is applied through gate 174 to gating amplifier 176 to discharge capacitor 170. When the intersection comes under control of this phase control unit, signal PFFU is no longer applied to amplifier 176.

If no call for right-of-way has been received from a conflicting traffic phase, the signal E no call passes through gates 162 and 164 of FIG. 5, becoming the maximum timer reset signal. This signal passes through gate 174 to gating amplifier 176, preventing voltage build-up on capacitor 170. When a call is received from a conilicting traic phase assigned to the same interval sequence unit, the signal E no call ends. When Va call is received from a conflicting traffic phase assigned to the other interval sequence unit, phase sequence unit 30 generates the signal call away Which is applied through OR gate 177 to block gate 162. In either case the maximum timer reset signal ends, and voltage builds up on capacitor 170 at a rate determined by the setting of adjustable resistor 172.

This maximum time voltage on capacitor 170 of the phase control unit of FIG. 4 is applied to the input of Schmitt trigger 178 Within the timing and gating circuitry of FIG. 5. When Schmitt trigger 17 8 fires, its output activates DC DMV 180. The output of DC DMV 180 passes through INHIBlTED-AND gate 181, becoming the signal go to preparatory. This signal is applied to line 181' of the interval sequence unit counter circuit (FIG. 3) to set the counter to its position 6, the preparatory position. The signal from gate 181 also passes through OR gate 156 and 164, generating the interval timer reset signal and the maximum timer reset signal. Thus, this maximum timer determines the maximum length of time for the part of the right-of-Way period overlapping positions 1-5 of the counter for the phase holding the right-of-way 13 against a car waiting on another phase, before the phase which has right-of-way is stepped to its green preparatory interval, position 6 of the counter.

In counter position 5, voltage is applied through variable resistor 182 within the phase control unit of FIG. 4 to one side of capacitor 183, theother side of which is grounded. OR gate 184 receives as inputs the signals from counter positions 2, 3, and 4. The output of OR gate 184 is applied to the input of gating amplifier 18S so that during counter positions 2, 3, and `4 gating amplifier 185 clamps capacitor 183 to ground. Then, when the counter moves to position 5, gating amplifier 185 unclamps the capacitor, and voltage passes through resistor 182 to build up upon the capacitor 183. Each time a vehicle passes through the detection zone of vehicle detector 102, DMV 108 sends a pulse through OR gate 110 and INHIBITED- AND gate 186 to the input of OR gate 184. As a consequence amplifier 185 turns on to discharge capacitor 183. OR gate 110 also receives an input directly from OR gate 106 so that if a vehicle is moving very slowly through the detection zone of vehicle detector 102 capacitor 183 will be held discharged for as long as the vehicle is within the detection zone. The output of the E vehicle timer circuit is applied from capacitor 183 through diode 188 to Schmitt trigger 190 within the interval sequence unit gating and timing circuitry of FIG. 5. The output of Schmitt trigger 190 is connected to one input of AND gate 192 which has the signal from gate 64 applied to its other input during counter position 5. Variable resistor 182 (FIG. 4) is adjusted so that the length of time required for the voltage on capacitor 183 to build up from ground potential to the firing level of Schmitt trigger 190 is substantially the same as the average time required for a vehicle to travel from vehicle detector 102 through the intersection.

GAP MEASUREMENT TIMER-FIGURE 6 In counter position a voltage is applied through resistor 194, shown in FIG. 6, to the first plate of capacitor 196 which has its second plate tied to ground. Thus, voltage builds up on capacitor 196. This voltage is applied through impedance converter 198 and resistor 200 to junction 202 which is tied to the input of Schmitt trigger 204. Impedance converter 198 acts as a buffer with high input impedance. When there is no call for right-of-way from a confiicting tratiic phase assigned to the same interval sequence unit, the signal 2 no call is applied to the signal input of INHIBITED-AND gate 205. If a call for right-of-way is present from a conflicting traffic phase assigned to the other interval sequence unit, the signal call away blocks gate 205. Thus, in the absence of calls for contiicting right-of-way, a signal from gate 205 passes through OR gate 206 to the input of gating amplifier 208. As a consequence, amplifier 208 clamps capacitor 196 to ground. When such a conicting call is received, this input to gate 206 terminates, and voltage commences to build up on capacitor 196. When a phase control unit is controlling the intersection, the signal PFFl is applied to the first input of its AND gate 209, shown in FIGURE 4. Each time a vehicle passes through the detection zone of vehicle detector 102, DMV 108 sends a pulse through OR gate 110 to the other input of gate 209. Coincidence of these two inputs causes gate 209 to generate a gap reset signal which is applied to the 2 gap reset input of OR gate 206 in FIG. 6. Thus, capacitor 196 is discharged each time a vehicle passes through the detection zone of the vehicle detector on a phase which is in control of the intersection. As a consequence, the voltage on capacitor 196 is a measure of the time spacing or gap between consecutive vehicles on that traffic phase.

During counter position 5, voltage also passes through variable resistor 210, within the phase control unit of FIG. 4, to the first plate of capacitor 212 which has its second plate tied to ground. So long as there is no call for right-of-way from a confiicting trafiic phase, the call away signal does not block INHIBITED-AND gate 213, and

so the 2 no call signal passes through gate 213 and through OR gate 214 to turn on gating amplifier 215 which clamps capacitor 212 to ground. Amplifier 215 is also held on by the signal PFFO via gates 128 and 214 when the intersection is under control of another traffic phase. Once a conliicting call is received, the output of gate 213 terminates, and so voltage commences to build up on capacitor 212. This voltage passes through diode 216 within the phase control unit to the E gap reduction timer input of impedance converter 217 within the interval sequence unit, as shown in FIG. 6, The output of impedance converter 217 is coupled through resistor 218 to junction 202 and thus to the input of Schmitt trigger 204. The voltage at junction 202 is a function of the sum of the voltage applied to the input of impedance converter 198 and the voltage applied to the input of impedance converter 217. This voltage at junction 202 is applied to the input of Schmitt trigger 204. The voltage at the input of impedance converter 217 continually increases after a confiicting right-of-way call is present during the vehicle interval (counter position 5). As the voltage at the input of impedance converter 217 increases, the difference between this voltage and the firing level of Schmitt trigger 204 decreases. This voltage difference represents the minimumV permissible gap between vehicles which will be permitted to retain right-of-way on this traffic phase. Hence the minimum permissible gap length continuously decreases once a conflicting call is received during the vehicle interval. When the voltage at the input of impedance converter 198 represents a gap exceeding the permissible minimum (i.e. the voltage at junction 202 exceeds the firing level of Schmitt trigger 204), Schmitt trigger 204 fires, and its output passes through INHIBIT- ED-AND gate 219 to set flip-iiop 220 to its one condition, thereby generating the signal last vehicle passage (LVP). This signal indicates that traffic on the phase having the right-ofway has reached such a light level that the gaps between consecutive vehicles exceed the minimum permissible gap, and so it is time to transfer right-of-way to the next phase which is awaiting it. OR gate 221 receives the hold signal and the counter position 1 signal at its input. The output of gate 221 is connected to the set zero input of flip-fiop 220, so that when the LVP signal causes transfer of right-of-way, flip-Hop 220 is reset to its Zero condition during counter position 1 of the next traffic phase.

The LVP signal is applied to the inhibit input of gate 186 within the phase control unit of FIG. 4. As a consequence, subsequent vehicles passing detector 102 do not cause capacitor 183 to be discharged. Therefore, the voltage at capacitor 183 increases until it reaches the firing level of Schmitt trigger 190, shown in FIG. 5 within the interval sequence unit. The output of Schmitt trigger passes sequentially through gates 192, 140, and 141 to activate Schmitt trigger 142 which turns on DC DMV 144. The DMV 144 output passes sequentially through gates 148, 150, and 152 to activate one-shot 154 which generates the advance pulse. This steps the counter of FIG. 3 to its position 6, the preparatory position.

Within the phase control unit of FIG. 4 voltage is applied through variable resistor 222 to one plate of capacitor 224 which has its other plate grounded. When this phase control unit is not controlling the intersection, the signal PFFO passes through OR gate 226 to turn on gating amplifier 228, clamping capacitor 224 to ground. When this phase control unit is controlling the intersection signal PFFO ends. Each time a vehicle passes detector 102, DMV 108 sends a pulse through gates 110 and 226 to turn on amplifier 228, thereby discharging capacitor 224. This discharging of cap-acitor 224 is not inhibited by the LVP signal. Thus, the voltage on capacitor 224 is a measure of the length of time which has elapsed since a vehicle has passed detector 102. The voltage on capacitor 224 passes through isolating diode 230 to the E passage timer input of Schmitt trigger 232 within the passage timing circuitry of FIG. 7. Schmitt trigger 232 has its output connected to the input of inverting amplifier 234, the output of which is tied to one input of AND gate 236. At its other input, gate 236 receives a signal from gate 68 during counter position 7, the vehicle clearance interval. Schmitt trigger 232 turns on when the voltage on capacitor 224 indicates that suicient time has elapsed since passage of a vehicle past detector 102 for that vehicle to have entered the intersection. Thus, whenever a vehicle is between detector 102 and the intersection, amplitier 234 applies an enabling input to gate 236. If that enabling input is present when counter position 7 is reached, a signal is generated by gate 236 to indicate that a vehicle will be waiting for right-of-way on this traic phase after right-of-way has been removed from the phase. Within the phase control unit of FIG. 4, this vehicle waiting signal is applied to one input of AND gate 238 which receives the signal PFFI at its other input. Gate 238 then sends a signal through OR gate 114 to set the phase memory tlip-op PMFF 116 to its one condition which indicates that right-of-way is to be returned to this traffic phase in its turn.

In the event that both phases on which right-of-way is present have reached their counter position number 5 and are to lose right-of-way, then a gap in the traffic ow on one phase in excess of the acceptable gap duration determined by the tiring level of Schmitt trigger 204 (FIG. 6) initiates that tralc phase stepping from counter position 5 to counter position 6. Gating circuitry within the phase sequence unit 30, to be discussed later, causes that tratlic phase to rest in this green preparatory counter position 6 until the other traffic phase has also reached its preparatory condition. The vehicle timing circuitry comprising resistor 182 and capacitor 183 insures that the last vehicle to pass the vehicle detector of the last traffic phase to come to the preparatory condition, has suflicient time to clear the intersection. However, since the other traic phase is resting in counter position 6, its vehicle timing circuit is not operating. Consequently, if a vehicle crosses its vehicle detector just before the second traiiic phase reaches its preparatory position, there might be insucient time for that vehicle to clear the intersection. In such an event, the passage timer comprising resistor 222 and capacitor 224 results in a signal being applied from gate 236 through gate 238 and gate 114 to set the phase memory tlip-tlop PMFF 116 so that right-of-way will be recalled to that traic phase. This insures that that Vehicle will not be trapped on a traffic phase to which right-of-way will not be returned.

The counter position 5 signal and the counter position 6 signal pass through OR gate 240 (FIG. 4) to the first input of AND gate 242 which receives the PFF1 signal at its second input. The output of gate 242 passes through OR gate 244 to reset phase memory flip-flop PMFF 116 to its zero condition. Thus, PMFF 116 is reset during interval 5 of the control sequence and is held reset during position 6. In addi-tion, the 2 green signal and the PF1-il signal pass through INHIBITED-AND gate 246, except with the LVP signal is applied to the inhibit input of gate 246. The output of gate 246 passes through OR gate 248 to block gate 112 so that. detector pulses cannot pass to the set one input of PMFF 116. If it is desired to provide the option of automatic recall of right-of-way to this traic phase, the PFFO signal is applied to one Contact of a vehicle recall switch 247, the other contact of which is applied through OR gate 114 to the set one input of PFF 116, as shown in FIG. 4.

Determination of which traffic phases are next to be allocated right-of-way takes place during the counter position 6 for those phases which are losing right-Of-way.. Thus, if a street change is to be made, requiring that bolh phases lose r-ight-of-way, the determination is made during the time that both counters are in their position 6. If one transfer is to be made on the salme street, then the determination is made when that one counter is in its position 6. To insure against erroneous indications during the brief time that the determination is made, the DMV 1.08 within each phase control unit is locked so that act-uations from vehicle detectors cannot be passed. Circui.ry within the phase sequence unit 30 generates the lock detector signal which is applied to each DMV 108 and through each OR gate 248 to the inhibit input of each IN- HlBITED-AND gate 112. When this signal is present, DMV 108 becomes a memory device. Thus, if at the time the lock detector signal is applied, DMV 108 is in its zero condition, it remains so until a vehicle detection pulse is applied to its set input from OR gate 106. Application of that pulse causes DMV 108 to assume its one condition, and it is locked in that one condition so long as the lock detector signal is present. Thus, DMV 108 remembers that a vehicle has passed its vehicle detector while the lock detector signal is present. When the couner steps out of its position 6 the lock detector signal ends, und the output from DMV 108 passes sequentially through gates 110, 112, and 114 to set PMFF 116 to its one condition, thereby indicating that a vehicle is waiting for rightof-way on that traic phase.

During the time that the counters in` both interval sequence units are in their positions 6, signals are applied through gating circuitry within the phase sequence unit to be described later to set the phase next flip-flop PNFF 118 with-in the phase control units of the next trafc phases which are to have right-of-Way. Phase control unit 30 then transmits the signal preparatory leave (PL) which is applied to OR gate Within the gating and timing circuitry (FIG. 5) of each interval sequence unit. This signal passes through OR gate 140, to cause the advance pulse from one-shot 154. As a consequence, the counter of FIG. 3 steps to its counter position 7, the vehicle clearance interval.

The vehicle clearance interval and the all-red interval of counter positions 7 and 8 are timed for durations determined by resistors 124 and 125, respectively, together with capacitor 127, and then the counter reaches its position 9, the transfer position. During counter position 9 phase sequence unit 30 generates a transfer signal which is applied to each interval sequence .unit which is to start a new cycle. Thus, if right-of-way is on tirst and second non-conicting tratiic phase and is to be transferred from the second phase to a third phase which is also non-conflicting with the first, the transfer signal is applied only to the interval sequence unit associated with the second and third phases. If instead right-of-way is to-be transferred to traic phases conicting with both `the tirst and second phases, the transfer signal is applied to both interval sequence units.

The transfer signal, shown in FIG. 5 as signal TR, is applied to OR gate 140 to turn on Schmitt trigger 142,

thereby causing one-shot 154 to generate an advance.

pulse. The TR signal is also applied through OR gate 166 to block gate 168 from passing the advance pulse to OR gate 164.

During the vehicle interval the counter position 5 signal from gate 64 (FIG. 3) passes through INHIBITED-AND gate 250 (FIG. 5) and OR gate 252 to the first input of AND gate 254. It there are no calls for right-of-way from traffic phases conicting with this tratlic phase, then INHIBITED-AND gate 256 passes a signal through OR gate 258 to the second input of gate 254. On coincidence of lthese two signals at gate 254, a'signal is applied to block gate from activataing one-shot 154 which gencrates the advance pulse. Thus, when trafc on all phases is extremely light, and the vehicle timer (comprising resistor 182, capacitor 183, and Schmitt trigger turns on Schmitt trigger 142, no advance pulse can be gener'- ated, unless there is actually a call for right-of-way from a conilcting tra'ic phase. As a consequence, the system will not slowly change back and forth, providing right-of- Way on one traflic phase and then on another tratlic phase during these extremely light traic conditions.

Within the phase control unit of FIG. 4, the signal PFFO passes through OR gate 260 to output line 262 which energizes the red indicator within trafiic signal 263 for this trafiic phase. The E green signal from inverter 76 associated with the counter circuitry is applied to one input of AND gate 264 within each phase control unit. When this phase control unit is controlling the intersection, the signal PFFI is applied to the second input of gate 264. As a consequence, gate 264 provides a signal on its output line 266 which is applied to the trafiic signal 263 at the intersection for this traiic phase to cause the green indication. AND gate 268 receives as inputs the signal PFFl and the signal from gate 68 during the counter position 7, the vehicle clearance interval. On coincidence of these two inputs, gate 268 provides a signal on output line 270 which ties to the traic signal 263 for this phase to cause the yellow indication. Lines 266 and 270 connect respectively to inverters 272 and 274 which have their outputs applied to the two inputs of AND gate 276. The output of AND gate 276 connects through OR gate 260 to output line 262 to cause the red indication during counter positions 8 and 9 when this phase control unit is controlling the intersection.

If this phase control unit is associated with one of the A traffic phases, which require pedestrian indications, then the pedestrian push-button shown in FIG. 4 as pedestrian push-button 278, is connected as an input to inverting amplifier 280. inverting amplifier 2-82 receives the lock detector input when the control system is determining which trafiic phase is next to be assigned rightof-way. Inverters 280 and 282 have their outputs applied to the two inputs of AND gate 284, thus inverter 282 applies a signal to gate 284 at all times except during the lock detector condition. Consequently, any time a pedestrian push-button is activated, except during this brief interval, inverter 280 passes a signal through gate 284 to OR gate 286 which applies the signal to the set one input of pedestrian phase memory flip-flop (PPMFF) 288. The start signal received when the control system -rst commences operation is also applied as an input to OR gate 286. Similarly, if it is desired to provide automatic recall to the pedestrian indications on this trafiic phase, then the signal PFFO is connected to one terminal of a pedestrian recall switch 289 which has its second terminal connected to the input of OR gate 286, as depicted in FIG. 4.

The one output of PPMFF 288 is connected as an input of OR gate 117, which also receives an input from the one output of PMFF 116. The output of OR gate 117 is the PMFFl signal, indicating that a call has been received for right-of-way on this trafiic phase. The one output of PPMFF 2-88 is also connected as an input to AND gate 290 which receives the signal PFFl as its other input. When these two inputs are applied to gate 290, the gate generates the pedestrian call signal for this phase which passes through isolating diode 292 to 2 pedestrian call circuitry. INHIBITED-AND gate 294 has its signal input tied to the one output of PPMFF 288 and its inhibit input connected to the one output of PFF 120. The output of gate 294 passes through inverting amplifier 296 to one input of AND gate 117'. Thus, in the absence of a call for pedestrian indications on this phase, no signal is applied from gate 294 to inverter 296. As a consequence the inverter 296 applies an input to gate 117'. If there has been no vehicle call for this phase, then PMFF 116 applies its zero output to the other input of gate 117', and gate 117 generates the no call signal for this phase which is applied through summing diode 297 to the E no call circuitry. When a pedestrian actuation has been received to set PPMFF 288 to its one condition, a signal is applied by gate 294 to inverter 296. As a consequence, the output from inverter 296 to gate 117 ends, and so the 2 no call signal is terminated. When this phase control unit is controlling the intersection,

18 then signal PFFI inhibits gate 294, and so inverter 296 again applies a signal to gate 117.

AND gate 298 receives a signal from gate 58 during counter position 2 at its first input and receives the PFFI signal from PFF 120 at its second input. Coincidence of these two inputs causes gate 298 to generate a signal on output line 300 to cause the pedestrian indicator 301 to provide the walk indication for the pedestrians on this tratiic phase. The output of gate 298 also resets PPMFF 288 to its zero condition. AND gate 302 receives a signal from gate 60 during counter position 3 at its first input and receives the signal PFF1 from PFF 120 at its second input. Coincidence of these two signals causes gate 302 to generate a signal on its output line 304 to cause the pedestrian indicator 301 to provide the pedestrian clearance indication for this trafiic phase. Output lines 300 and 304 are connected respectively through inverters 306 and 308, each of which has its output tied to an input of AND gate 310. The output of gate 310 is connected as one input to OR gate 312. INHIBITED- AND gate 314 receives the PFFI o-utput from PFF 120 at its signal input. The inhibit input of gate 314 is connected to the output of yfree-running multivibrator within the counting circuitry of FIG. 3 to receive flashing power during counter position 3. The output of gate 314 is connected to the input of inverter 316 which has its output tied to the second input of OR gate 312. The output of OR gate 312 is connected to output line 318 which causes the wait indication on the pedestrian indicator 301 for this trai-lic phase. If the pedestrian indicator utilized with this traffic phase has its own flashing power, then gate 314, inverter 316 and OR gate 312 can -be omitted, with the output line 318 taken directly from AND gate 310. Then during the pedestrian clearance interval of counter position 3, the pedestrian clearance indication on output line 304 activates this source of fiashing power within the pedestrian indicator to cause a iiashing dont walk or flashing wait indication for pedestrians. If the pedestrian indicator does not have its own source of ashing power, then output line 304 is not connected to the pedestrian indicator, but instead gates 312 and 314 and inverter 316 are provided as depicted in FIG. 4. During counter position 3 the lflashing power interrupts the application of the signal applied to gate 314. An intermittent signal on line 318 then causes the dont walk or wait indicator to flash on the pedestrian indicator 301. During all counter positions except counter positions 2 and 3 for this traiiic phase, inverters 306 and 308 both apply signals to AND gate 310 which then passes an indication through gate 312 to cause the wait indication to appear on the pedestrian indicator 301. For the phase control units associated with the B trafiic phases which do not require pedestrian indications, the components 117, 117', and 278-318 of FIG. 4 are omitted.

PHASE SEQUENCE UNIT COMMON CIRCUITRY FIGURE 8 FIG. 8 depicts circuitry within phase sequence unit 30 which determines when the counters within each interval sequence unit are to be stepped out of the preparatory interval of counter position 6 to the clearance interval of counter position 7. If a street change is to be made, this phase sequence unit common circuitry synchronizes operation of the two counters, thereby insuring that the right-of-way periods end at the same time on both traffic phases of the street losing right-of-way.

When the green right-of-way for a trafiic phase is to end, a preparatory leave signal is generated within this common circuitry. A preparatory leave signal is generated for each interval sequence unit. These signals are shown as signal ISO-PL, obtained from AND gate 402 to signify that the odd interval sequence unit should leave its preparatory position, and as signal ISE-PL obtained from AND gate 404 to signify that the even interval sequence unit should leave its preparatory position.

Under extremely light traic conditions, right-of-way might be assigned for a long period of time to the two straight-through tratiic phases of one street, for example, phases A1 and A2 of street I, with each interval sequence unit resting in its counter position 5. If there is then received a call for right-of-way from only one coniiicting traic phase such as phase A3, both interval sequence units step sequentially through their positions 6, 7, and 8 to position 9, the transfer position. The odd interval sequence unit associated with phase control unit A3 then steps to its position 1 to assign right-of-way to traic phase A3. However, there has not been a call for right-of-way on any even traiiic phase and so the even interval sequence unit does not have a phase control unit requiring right-ofway. Accordingly, the even interval sequence unit rests in counter position 9, the transfer position. This condition of having right-of-way assigned to only one traic phase is referred to as single-ended operation as distinguished from double-ended operation in which right-of- Way is simultaneously provided to two non-coniiicting traffic phases. The phase sequence unit common circuitry of FIG. 8 includes flip-flop 400 which is set to its one condition when single-ended operation results in right-ofway being provided for an even trai-lic phase but not for an odd traic phase, Thus, ip-iiop 400 is referred to as the odd interval sequence no call hip-flop (ISONCFF), and it provides the signal ISONCFFI during even phase single-ended operation. Similarly, iiip-ilop 401 is the even interval sequence no call flip-flop (ISENCFF) and it provides the signal ISENCFF 1 during odd phase single-ended operation.

R gate 405 receives as inputs the one output of the phase next hip-flop 118 in each odd phase control unit. Thus, gate 405 receives as inputs the signals AIPNFFI, BlPNFFl, A3PNFF1, and BSPNFFI. In addition, when the traic control system is in even phase single-ended operation, OR gate 405 receives as an input the signal ISONCFFI from the no call flip-Hop 400 for the odd interval sequence unit. The output of gate 405 is applied as an input to AND gate 402. The second input to gate 402 is the counter position 6 signal ISO(6) from gate 66 within the odd interval sequence unit. On coincidence of these two inputs to gate 402, the gate generates the signal ISO-PL, causing the odd interval sequence unit to leave its preparatory position. In like manner, OR gate 406 receives as inputs the signals A2PNFF1, BZPNFFI, A4PNFF1, and B4PNFF1 from the phase next flip-Hop 118 Within each even phase control unit. In addition, OR gate 406 receives the input signal ISENCFFI during odd phase single-ended operation, when there is no even phase control unit controlling the intersection. The output of gate 406 is connected as an input to AND gate 404. When the counter within the even interval sequence unit is in its position 6, gate 404 receives the ISE(6) signal from AND gate 66 within that even interval sequence unit. Ou coincidence of these two inputs, gate 406 generates the ISE-PL signal, indicating that the even interval sequence unit is to leave its preparatory position.

The preparatory leave signal PL is applied to OR gate 140 within the gating and timing circuitry of FIG. 5, causing one-shot 154 to generate the advance pulse.

STREET CHANGES The one output of the phase memory flip-op 116 associated with each street II traffic phase is applied as an input to OR gate 408, shown in the upper left of FIG. 8. Thus, gate 408 receives the signal A3PMFF1, A4PMFF1, BSPMFFI, and B4PWFF1. The output of gate 408 is the signal 34-4 call. This signal is applied to each set of phase selection circuitry for use as depicted in FIG. 9. In addition, the output of gate 408 is connected to the input of inverter 409 which has its gutput applied to each set of phase selection circuitry to provide the signal TS-(, ca ll when there is ne input t0 gate 408.

The output of gate 408 is connected as an input to AND gate 410. Gate 410 also receives as inputs the signals A1PFF1 and ISO(16). Thus, when right-of-way is on phase A1 and the odd interval sequence unit has stepped to its preparatory position, a call for right-of-way from any street II traiiic phase results in a signal passing from gate 410 through OR gate 412 to the rst input of AND gate 414. AND gate 416 receives as inputs the signals BIPFF 1 AIPMFFO, and ISO(6). Thus, if right-of-way is on phase B1 and there has been no call for right-of-way from phase A1, but the odd interval sequence is in its preparatori position, then gate 416 generates a signal which also passes through OR gate 412. to the first input of AND gate 414.

AND gate 418 receives as inputs the signals A2PFF1, lSE(6), and 3+4 call. Therefore, if right-of-way is on traflic phase A2, and there has been a call for right-ofway from a street II traffic phase, and the even interval sequence unit is in its preparatory position, gate 418 passes a signal through OR gate 420 to the second input of AND gate 414. Likewise, AND gate 422 receives as inputs the signals BZPFFI, A2PMFFO, and ISE(6). Therefore, if right-of-way is on traffic phase B2 and there has not been a call for right-of-way from phase A2 Ibut the even interval sequence unit is in its preparatory position, then gate 422 generates a signal which also passes through OR gate 420 to the second input of AND gate 414.

Coincidence of the two inputs to AND gate 414 indi- Cates that right-of-Way is on traffic phases found on street I and is about to be transferred to traic phases of street II` In this condition, gate 414 passes a signal through OR gate 424 which is then applied to OR gate 426. The output of gate 426 is the lock detector signal applied to the vehicle detector DMV 108 via OR gate 248 to the inhibit input of gate 112 within each phase control unit to prevent the output of DMV 108 from passing during the preparatory interval.

The output of OR gate 424 is also applied to the input of time delay 428 which provides a delay in the order of 40 milliseconds. The output of delay 428 is applied to the input of Schmitt trigger 430. The Schmitt trigger 430 output is the signal street I to street II change. This signal indicates that right-of-way is to be transferred from street I to street II and is applied to each set of phase selection circuitry for use as shown in FIG. 9. Within the phase selection circuitry the street I to street II change signal is utilized to cause the commands which set to the one condition the phase next ilip-op 118 within the appropriate phase control unit, as explained more fully hereinafter with reference to FIG. 9. Time delay 428 is provided to insure that each DMV 108 has locked before the phase selection circuitry decides which phase next ip-ilops are to be set.

A corresponding set of circuitry is provided to gencrate the street II to street I change signal. Thus, OR gate 432 receives as inputs the signals AIPMFFI, AZPMFFI, BIPMFFI, and BZPMFFI from the phase memory flip-flops within each street I phase control unit. These signals are present Whenever a call for right-ofway is received on the associated street I trafiic phase. The output of gate 432 is the signal 1+2 call indicating that a call for right-of-way has been received from one of the street I traic phases.

.This signal is applied to each set of phase selection circuitry for -use as depicted in FIG. 9. In addition, the output of gate 432 is connected to the input of inverter 434 which has its output applied to each set of phase selection circuitry. This output is the signal -lom which is present when there is no input to gate 432.

The .output of OR gate 432 is also connected as an input to AND gate 436. Gate 436 also receives as inputs the signals A3PFF1 and ISO(6). Thus, when right-of-way is on trafc phase A3 and a call for right-o-Way has been received from one of the street I traiiic phases and the odd interval sequence unit is in its preparatory position, gate 436 passes a signal through O R gate 438 t0 the 21 first input of AND gate 440. AND gate 442 receives as inputs the signals B3PFF1, ASPMFF() and ISO(6). Therefore, when right-of-way is on traffic phase B3 and there has not `been a call for right-of-way on traic phase A3, but the odd interval sequence unit is in its preparatory position, gate 442 provides a signal which also passes through OR gate 438 to the first input of AND gate 440.

AND gate 444 receives as input the signals A4PFF1, ISE(6), and l-t-Z call. Thus, if trafc phase A4 is providing right-of-way and a call is received for right-ofway from a traic phase on street I and the even interval sequence unit is in its preparatory position, a signal from gate 444 passes through OR gate 446 to the second input of AND gate 440. AND gate 448 receives as inputs the signals B4PFF1, A4PMFFO and ISE(6). Therefore, if right-of-way is on traic phase B4 and there is no call for right-o-way from trafic phase A4, but the even interval sequence unit is in its preparatory position then gate 448 provides a signal which also passes through OR gate 446 to the second input of AND gate 440. Coincidence of these two inputs to -gate 440 indicates that right-of-way is on street II and is to be transferred to street I. In this condition, gate 440 provides a signal which passes through OR gate 450 to OR gate 426. The output of OR gate 426 is the lock detector signal which causes the DMV 108 within each phase control unit to lock, as described above.

The output of gate 450 also is connected to the input of time delay 452, which may be in the order of 40 milliseconds. The output of time delay 452 is connected to Schmitt trigger 454 which provides as its output the signal street II to street I change. This signal is applied to each set of phase selection circuitry for use as depicted in FIG. 9. This signal passes through gating within the phase selection circuitry to cause the appropriate phase next ip-op to be set to its one condition;

If a single-ended call for right-of-way has been received, then only one phase next Hip-flop will be set to its one condition. For example, if right-of-way is on traic phases A1 and A2 when a call for right-of-way is received from traffic phase A3, then the street I to street II change signal is generated and passes through logic within the odd phase selection circuitry of FIG. 9 to cause the phase next ilip-op within phase control unit A3 to be set to its one condition. As a consequence the signal A3PNFF1 is applied through OR gate 405 to AND gate 402. The ISO(6) signal is also applied to AND gate 402, and so gate 402 generates the signal ISO-PI., causing the counter within the odd interval sequence unit to leave its preparatory position and to commence the vehicle clearance interval of counter position 7. However, since there has not been a call for right-of-way from au even traffic phase, the even phase selection circuitry does not cause any of the phase next ip-ops within the even phase control units to be set to their one condition. Accordingly, there is no signal from any of the phase next ip-ops applied to OR gate 406. In the condition described in the illustrative example above, gate 418 provides a signal through OR gate 420 to one input of AND gate 456. The street I to street II change signal is also applied to gate 456. Since there has not been a call for right-of-way on either phase A4 or phase B4, both the A4PMFFO signal and the B4PMFFO signal are applied to gate 456. As a consequence, gate 456 generates a signal which passes through OR gate 458 to set to its one condition ISENCFF 401, the no-call ilip-op associated with the even interval sequence unit. This provides the signal ISENCFFI which passes through OR gate 406 to AND gate 404. Since the even interval sequence unit is in its preparatory position, the signal ISE(6) is also applied to gate 404, and so gate 404 provides the ISE-PL signal, causing the even interval sequence unit to leave its preparatory position, and to enter the vehicle clearance interval of counter position 7.

In like manner, if right-of-way is on street II when a call for right-of-way is received from a single street I tralic phase, such as trafc phase A1, then the output of gate 446 is applied to the input of AND gate 460. The street II to street I change signal is also applied to gate 460. Since there has not been a call for right-ofway from either phase A2 or phase B2, both the signal A2PMFFO and the signal B2PMFFO are applied to gate 460. As a consequence, gate 460 generates a signal which passes through OR gate 458 to the set one input of ISENCFF 401. Thus, the system is again placed in singleended operation.

When the system returns to double-ended operation, the even interval sequence unit steps to its counter position 1, and inverter 76 within the even interval sequence unit applies the ISE E green signal to the signal input of INHIBITED-AND gate 462. During the preparatory position of the even counter, the ISE(6) signal is applied to the inhibit input of gate 462. Thus, when the green indication is returned to an even traflc phase, gate 462 generates a signal which returns ISENCFF 401 to its zero condition.

In like manner, when the system is in single-ended operation on an even traic phase, ISONCFF 400, the no call flip-lop for the odd interval sequence, is set to its one condition. Thus, the output of OR gate 412 is applied as an input to AND gate 464 which also receives as inputs the signals A3PMFFO, B3PMFFO, and street I to street II change. The output of gate 464 passes through OR gate 466 to the set one input of ISIONCFF 400. Consequently, the signal ISONCFFI passes through OR gate 405 to the vfirst input of AND gate 402, and so when even phase single-ended operation is to take place, this input enables gate 402 to transmit the signal ISO-PL to cause the odd interval sequence unit to leave its preparatory position. The output of OR gate 438 is connected as an input to AND gate 470 which also receives as inputs the signals A1PMFFO, B1PMFFO, and street II to street I change. The output of gate 470 passes through OR gate 466 to cause ISONCFF 400 to assume its one condition. When double-ended operation is resumed and the green indication is provided for an odd traic phase, the output of inverter 76 within the odd interval sequence unit is applied as the ISO E green signal input to INHIBITED-AND gate 472. During the odd counter position 6 the signal ISO(6) is applied to the inhibit input of gate 472. Thus, when the green indication is returned to an odd traffic phase, the output of gate 472 is applied to the set zero input of ISONCFF 400 to return the iiipop to its zero condition.

The transfer from single-ended operation on one street to double-ended operation on the other street requires that the appropriate street change signal be generated. Accordingly, OR gate 474 in FIG. 8 receives as inputs the counter position 9 signals from both the odd interval sequence unit and the even interval sequence unit and applies its output to AND gate 476. OR gate 478 receives the counter position 6 signal from both interval sequence units and `applies its output to AND gate 476. OR gate 480 receives the one output from both no call ip-op; thus it receives as inputs the signals ISONCFFl and ISENCFFI. The output of gate 480 is connected to an input of AND gate 476. OR gate 482 receives as inputs the B/A call signals from each set of phase selection circuitry. This signal is generated in each set of phase selection circuitry when right-of-way on a left-turn traic phase is to be terminated and transferred to straightthrough trafc from the opposite direction on the same street, as more fully explained hereinafter with reference to FIG. 9.

The output of gate 482 is connected to the input of inverter 484 which has its output tied to an input of AND gate 476. The output of gate 476 is applied as an input of AND gate 486 which also receives as inputs the signals A3PFFO, B3PFFO, A4PFFO, and B4PFFO. Thus, if right-of-way is on a street I traffic phase, these latter four signals are applied to gate 486. During single-ended operation the interval sequence unit associated with the traflic phases which are not providing any right-of-Way is in its counter position 9, and so a signal passes from gate 474 to gate 476. One of the no call flip-flops 400 or 401 is in its one condition, and so a signal passes from gate 480 to gate 476. When the trafhc phase which is providing right-of-Way reaches its counter position 6, a signal passes from gate 478 to gate 476. If right-of-Way is to be transferred to another street, then there is no B/A call signal, and so inverter 484 applies a signal to gate 476. Consequently, gate 476 applies a signal to gate 486, and so gate 486 passes a signal through OR gate 424 to gate 426 to cause the lock detector signal. In addition, this v signal passes from gate 424 to time delay 428 which introduces a short delay before turning on Schmitt trigger 430 to generate the street I to street II change signal.

In like manner, the output of gate 476 is applied to gate 488 which receives the signals A1PFFO, B1PFFO, AZPFFO, and BZPFF() as inputs. Thus, if the system is in single-ended operation on a traffic phase of street II, and it is to change to a street I trahie phase, gate 488 provides a signal which passes through OR gate 450 to gate 426 where it becomes the lock detector signal. In addition, the signal from gate 450 is applied. to time delay 452 which introduces a short delay before turning on Schmitt trigger 454 to generate the street II to street I transfer signal.

These street change signals are applied through gates Within each set of phase selection circuitry to set to the one condition phase next flip-flop 118 Within the appropriate phase control units.

PHASE SELECTION CIRCUITRY--FIGURE 9 FIG. 9 depicts the odd phase selection circuitry within phase sequence unit 30. This odd phase selection circuitry determines which odd trailic phase is next to be assigned right-of-way. A corresponding set of circuits is provided within the even phase selection circuitry to receive the corresponding input signals and to provide the corresponding output signals.

AND gate 502 Within the odd phase selection circuitry of FIG. 9, receives as an input the signal BIPFFI when the phase control unit associated with tralc phase B1 is controlling the intersection. The second input of gate 502 receives the signal AlPMFFl when a call for right-of- Way has been received from trahie phase A1. The last input of gate 502 receives a signal from AND gate 66 within the odd interval sequence unit during odd counter position 6. This signal is designated ISO(6) and exists during the green preparatory period. Thus, gate 502 provides an output during the odd preparatory period when right-of-way is on phase B1 and a call for right-of-Way has been received from phase A1. This output from gate 502 passes through OR gate 504 to iire Schmitt trigger 506 which provides the signal AIPNFFSI that is applied to the set one input of PNFF 118 within the phase control unit associated with traffic phase A1.

In like manner, AND gate S08 receives at its first input the signal B3PFF1 when the phase control unit associated with traic phase B3 is controlling the intersection. The A3PMFF1 signal is applied to the second input of gate 508 when a call for right-of-way has been received from traffic phase A3. When the odd interval sequence unit is in its green preparatory position of counter position 6, the ISO(6) signal is applied to the third input of gate 508. The output of gate 508 passes through OR gate 510 to re Schmitt trigger 512 which provides the A3PNFFS1 signal that sets PNFF 118 within the phase control unit associated with trailic phase A3 to its one condition.

The output of gate 502 indicates that right-of-way is to transfer from phase B1 to phase A1, both of which are non-conicting With phase A2. Similarly, the output of gate 508 indicates that right-of-way is to transfer' from phase B3 to phase A3, both of which are non-coniiicting with phase A4. When such a transfer is made in the odd interval sequence unit, no transfer is required on the even traic phases. Accordingly, the output of AND gate 502 and the output of AND gate 508 are passed through OR gate 513, becoming the signal B/A call which is applied to the common phase sequence unit circuitry of FIG. 8.

When the phase control unit associated with traffic phase A1 is controlling the intersection, the signal AlPP-'Fl is applied to the rst input of AND gate 514. The ISO(6) signal is applied to the second input of gate 514 during the preparatory interval of the odd interval sequence unit. If there has not been a call for right-ofway from street II, then the signal -l- Ea is applied to the third input of gate 514. If the odd interval sequence unit has been stepped to its preparatory position While right-of-vvay is assigned to traiic phase A1 and there has not been a call for right-of-way from street II, then it must be required that right-of-Way be transferred to phase B1. Accordingly the output of gate 5'14 passes through OR gate 516 to tire Schmitt trigger 518, generating the signal B1PNFFS1 which is applied to set one input of PNFF 118 within the phase control unit associated with traffic phase B1.

Similarly, the signal A3PFF1 is applied to the rst input of AND gate S20 when phase control unit A3 is controlling the intersection. The ISO(6) signal is applied to the second input of gate 520 during the preparatory interval of the odd interval sequence unit. If there has not been a call for rightof-way on street I, then the signal cl is applied to the third input of gate 520. Accordingly, gate 520 provides an output when the odd interval sequence unit is in its preparatory interval prepar ing to transfer right-of-way to another phase and when right-of-Way is presently on phase A3, in the absence of a call from street I. This condition means that right-of-way is next to be transferred to phase B3. Accordingly, the output of gate 520 passes through OR gate 522 to re Schmitt trigger 524, the output of which passes through OR gate 526 to become the signal B3PNFFS1 which is applied to the set one input of PNFF 118 Within the phase control unit associated with traic phase B3. The start signal is also applied to the input of OR gate S26, so that, when the control system is first placed into operation, it commences with the intersection under the control of phase control unit B3.

AND gate 528 receives as its iirst input the signal AIPMFFI when a call has been received for right-of-way on the trailic phase A1. The second input to AND gate 528 is the signal BIPMFFO which is present when there has not-been a call for right-of-way on traflic phase B1. When the common portion of the phase control unit depicted in FIG. 8 indicates that right-of-Way is to be transferred from street Il to street I, an input is applied to the third input of gate 528. On coincidence of these three inputs, gate 528 transmits a signal through OR gate 504 to iire Schmitt trigger S06, thereby generating the signal AIINFFSL The street II to street I change signal is also applied as an input to AND gate 530 which receives as its second input the signal B1PMFF1 when a call for right-of-way has been received from traffic phase B1` Coincidence of these two signals causes gate 530 to transmit a signal through OR gate 516 to iire Schmitt trigger 518 generating the signal BlPNFFSl which indicates that right-ofway is next to be assigned to phase B1. Thus, phase B1 is given priority over phase A1, and when a street II to street I change is to be made, if a call for right-of-Way has been received from trafic phase B1, right-ofway is rst assigned to that phase, whether a call has been received from phase A1 or not. However, if no call has been received from phase B1 but a call has been received for right-of-way from phase A1, then right-of-vvay is assigned to phase A1.

25 Similarly, AND gate 532 receives as its first input the signal A3PMFF1, as its second input the signal B3PMFFO and as its third input the street I to street II change signal provided by the common phase sequence unit circuitry of FIG. 8. On coincidence of these three signals gate 532 passes a signal through OR gate 510 to fire Schmitt trigger 512, thereby generating the signal A3PNFFS1 which indicates that right-of-way is next to be assigned to phase A3. AND gate 534 receives as its first input the street I to street II change signal and as its second input the signal B3PMFF1. Gate 534 passes its output through OR gate 522 to fire Schmitt trigger 524 which indicates that rightof-way is next to be assigned to trafc phase B3. Hence, when the street I to street II change signal indicates that right-of-Way is to be transferred to street II, and a call for right-of-Way has been received from traic phase B3, that traic phase is next assigned right-of-Way, whether a call has been received from phase A3 or not. But, in the absence of a call for right-of-way from phase B3 and in the presence of a call for right-of-way from phase A3, then phase A3 is next assigned right-of-Way.

TRANSFER GATING CIRCUITRY-FIGURE Phase sequence unit 30 includes two sets of gating circuitry which generate the transfer commands for the two interval sequence units. FIG. 10 depicts the circuitry which generates the signal ISO-TR to cause the odd interval sequence unit to transfer control of the intersection from one odd phase control unit to another. A corresponding set of gating generates the transfer signal ISE-TR for the even interval sequence unit.

OR gate 536 in FIG. 10 receives as inputs the signals AlPNFFl and B1PNFF 1 when either Schmitt trigger 506 or Schmitt trigger 518 of FIG. 9 has caused the phase next ip-flop PNFF 118 of phase A1 or PNFF 118 of phase B1 respectively, either of which is illustrated in FIG. 4, to set to its 1 condition. This output from gate 536 is applied as an input to AND gate 538. Gate 538 also receives as inputs the signals A4PFFO and B4PFFO to indicate that the phase control units associated with traic phases A4 and B4 are not controlling the intersection. In like manner the signal A3PNFF1 and the signal B3PNFF1 are applied as inputs to OR gate 540 when the phase next ip-flop in the phase control unit associated with either phase A3 or phase B3, respectively, is in its one condition. The output of gate 540 is connected to one input of AND gate 542 which receives at its other inputs the signals A2PFFO and BZPFF() when phase control units A2 and B2 are not controlling the intersection. The outputs of the gates 538 and 542 pass through OR gate 544 to one input of AND gate 546. The other input of gate 546 is connected to the output of gate 72 associated with the counter of the odd interval sequence unit, shown in FIG. 3. This signal ISO(9) indicates that the counter Within the odd interval sequence unit is in its transfer position 9.

The phase next flip-flop 11S (FIG. 4) within the phase control unit of the trac phase which is to be assigned right-of-Way is set to its one condition during the preparatory interval of counter position 6. During the transfer interval of counter position 9, the phase flip-flop 120 within each phase control unit is setto its zero condition. Accordingly, during counter position 9, the signals AZPFFO, BZPFFQ, A4PFFO, and B4PFFO are all present. If for example, the right-of-way has been called to phase A3, then the phase next flip-flop 118 within the phase control unit associated with traffic phase A3 is set to its one condition, and so the signal A3PNFF1 passes through OR gate S40 (FIG. l0) to AND gate 542. As a consequence, gate 542 passes its output through gate 544 to one input of AND gate 546. Thus, when the ISO(9) signal is applied to gate 546, this gate generates the transfer signal for the odd interval sequence unit, referred to as signal ISO-TR. This transfer signal is applied to gates and 166 within the gating and timing circuitry associated with the odd interval sequence unit, as shown in FIG. 5. As a consequence, the odd interval sequence unit generates an advance pulse to step its counter to position 1, thereby initiating the control period for phase control unit A3. The even phase selection circuitry of the phase sequence unit 30 contains corresponding gates which under corresponding conditions provide the ISE-TR signal which is applied to the even interval sequence unit to step that counter from its transfer position 9 to its skip position 1.

If a call for single ended operation is received, only one transfer signal is generated. For example, if a call for even phase single ended operation is received, no odd phase next tiip-op set one signal is generated. Accordingly, neither OR gate 536 nor OR gate 540 provides an output. Consequently, gate 546 cannot transmit the ISO- TR signal, and so the odd interval sequence unit rests in its counter position l9, causing red indications on all of its trafc phases, While the even interval sequence unit steps through its regular sequence. When this happens the odd no call flip-flop ISONCFF, within the common circuitry of the phase sequence unit, is set to its one condition, providing the signal ISONCFFl, as depicted in FIG. 8.

TRANSFER FROM SINGLE-ENDED TO DOUBLE- ENDED OPERATION ON THE SAME STREET- FIGURE 9 When the tratiic control system is operating in even phase single ended operation and a call for right-of-way is received from a non-conflicting traic phase on the same street, AND gate 54S provides a pulse which is passed through appropriate gating circuitry to re the appropriate Schmitt trigger 506, 512, 518, or 524 which generates a signal to set the phase next iiip-op 118 in the phase control unit to which right-of-way is to be called. The rst input to gate 548 is applied from OR gate 550 which receives as inputs the signals from the memory flip-flops of the odd trac phases. Thus the signals AlPMFFl, BlPMFFl, A3PMFF1, and B3PMFF1 are applied as inputs to gate 550, and whenever a call is present for right-of-way on one of the odd traflic phases, gate S50 applies an input to AND gate 548. The signal AZPFFI is applied as an input to OR gate 552 which receives as its other input the signal B2PFF1. Thus whenever either phase control unit A2 or phase control unit B2 is controlling the intersection, a signal passes from OR gate 552 to the first input of AND gate 554.

The signals A2PNFF1 and B2PNFF1 are provided as inputs to OR gate 556. The output of gate 556 is connected to the Second input of AND gate 554. Gate 554 has its output connected through OR gate 558 to one signal input of INHIBITED-AND gate 560. The second signal input of gate 560 receives the signal ISONCFFI during even phase single ended operation. The even interval sequence unit advance pulse is applied to the inhibit input of gate 560 so that during this advance pulse gate S60 cannot permit passage of its output signal.

INHIBITED-AND gate 562 receives the E green signal from inverter 76 Within the even interval sequence unit. The inhibit input of gate 562 receives the counter position 6 signal from gate 66 Within the even interval sequence unit. Therefore, gate 562 provides an output signal during counter positions 1-5 of the even interval sequence unit. This output from gate 562 is connected as an input to OR gate 558.

In a similar manner, OR gate 564 receives as inputs the signals A4PFF1 and B4PFF1 and applies its output to one input of AND gate 566. OR gate 568 receives as inputs the signals A4PNFF1 and B4PNFF1 and provides its output to the second input of gate 566. The output of gate 566 is connected as an input of OR gate 558.

During even phase single ended operation, the signal ISONCFFI is applied as an input to INHIBITED-AND

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