JPS62186433U - - Google Patents
Info
- Publication number
- JPS62186433U JPS62186433U JP7415486U JP7415486U JPS62186433U JP S62186433 U JPS62186433 U JP S62186433U JP 7415486 U JP7415486 U JP 7415486U JP 7415486 U JP7415486 U JP 7415486U JP S62186433 U JPS62186433 U JP S62186433U
- Authority
- JP
- Japan
- Prior art keywords
- glass
- glass layer
- insulating base
- main surfaces
- lid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 230000003746 surface roughness Effects 0.000 claims 1
Landscapes
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案のガラス封止形半導体パツケー
ジの一実施例を示す分解斜視図、第２図は第１図
のガラス封止形半導体パツケージの封止後の断面
図である。
１……絶縁基体、２……蓋体、４……半導体素
子、５……外部リード端子、６ａ，６ｂ……ガラ
ス層、７……電極。
FIG. 1 is an exploded perspective view showing an embodiment of the glass-sealed semiconductor package of the present invention, and FIG. 2 is a sectional view of the glass-sealed semiconductor package of FIG. 1 after being sealed. DESCRIPTION OF SYMBOLS 1... Insulating base, 2... Lid, 4... Semiconductor element, 5... External lead terminal, 6a, 6b... Glass layer, 7... Electrode.
Claims (1)
体と蓋体とで外部リード端子を挾持し、前記ガラ
ス層を溶融一体化することにより半導体素子を内
部に気密封止するガラス封止形半導体パツケージ
において、前記絶縁基体及び蓋体の主面に被着さ
せたガラス層の表面粗さをＲｍａｘ５．０μｍ以
下としたことを特徴とするガラス封止形半導体パ
ツケージ。 A glass-sealed type in which an external lead terminal is sandwiched between an insulating base and a lid whose main surfaces that face each other are covered with a glass layer, and the semiconductor element is hermetically sealed inside by melting and integrating the glass layer. 1. A glass-sealed semiconductor package, characterized in that the glass layer deposited on the main surfaces of the insulating base and the lid has a surface roughness Rmax of 5.0 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7415486U JPH043499Y2 (en) | 1986-05-16 | 1986-05-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7415486U JPH043499Y2 (en) | 1986-05-16 | 1986-05-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62186433U true JPS62186433U (en) | 1987-11-27 |
| JPH043499Y2 JPH043499Y2 (en) | 1992-02-04 |
Family
ID=30919115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7415486U Expired JPH043499Y2 (en) | 1986-05-16 | 1986-05-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH043499Y2 (en) |
-
1986
- 1986-05-16 JP JP7415486U patent/JPH043499Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH043499Y2 (en) | 1992-02-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62186433U (en) | ||
| JPH0375537U (en) | ||
| JPS6019229U (en) | piezoelectric oscillator | |
| JPS61134046U (en) | ||
| JPS62177039U (en) | ||
| JPH0351844U (en) | ||
| JPH045650U (en) | ||
| JPS6190255U (en) | ||
| JPH0351845U (en) | ||
| JPS62103252U (en) | ||
| JPS59191707U (en) | Glass sealed thermistor | |
| JPH01162246U (en) | ||
| JPS6439643U (en) | ||
| JPS58138342U (en) | Glass-sealed semiconductor package | |
| JPS6340020U (en) | ||
| JPS59127247U (en) | Glass sealed semiconductor device | |
| JPS62164417U (en) | ||
| JPS61153346U (en) | ||
| JPS6335313U (en) | ||
| JPS61157334U (en) | ||
| JPH033753U (en) | ||
| JPH0427623U (en) | ||
| JPS6367204U (en) | ||
| JPS58135945U (en) | Glass-sealed semiconductor package | |
| JPS6071106U (en) | voltage nonlinear resistance porcelain |