JPS62183146A - Ceramic package for semiconductor device - Google Patents

Ceramic package for semiconductor device

Info

Publication number
JPS62183146A
JPS62183146A JP2533486A JP2533486A JPS62183146A JP S62183146 A JPS62183146 A JP S62183146A JP 2533486 A JP2533486 A JP 2533486A JP 2533486 A JP2533486 A JP 2533486A JP S62183146 A JPS62183146 A JP S62183146A
Authority
JP
Japan
Prior art keywords
weld ring
cavity
weld
ring
ceramic package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2533486A
Other languages
Japanese (ja)
Inventor
Masao Ueda
植田 正夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2533486A priority Critical patent/JPS62183146A/en
Publication of JPS62183146A publication Critical patent/JPS62183146A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve a weld ring mounting accuracy by forming a weld ring positioning projection or recess on the upper surface of the periphery of a cavity of fixing a semiconductor element of a ceramic substrate to eliminate a weld ring mounting exclusive jig. CONSTITUTION:A weld ring 4 is bonded to the upper surface of the periphery of the cavity 2 of a ceramic substrate 1. The positioning projection 3 of the ring 4 is formed along a pair of opposed inside surface of the ring 4 of a square shape. The ring 4 may be positioned just in engagement in a recess 6 formed on the upper surface of the periphery of the cavity 2 for fixing a semiconductor element of a ceramic substrate 5. Thus, a weld ring mounting exclusive jig is eliminated, and the weld ring mounting accuracy can be enhanced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置用セラミックパッケージに関し、
特にウェルドリングを有する半導体装置用セラミックパ
ッケージに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a ceramic package for a semiconductor device,
In particular, the present invention relates to a ceramic package for semiconductor devices having a weld ring.

〔従来の技術〕[Conventional technology]

従来、この檻の半導体装置用セラミックパッケージは、
第3図の断面図に示すよりに、中央部に半導体素子を固
定するためのキャビティ2を有するセラミック基体11
のキャビティ2の周囲の上面には、キャビティ2に半導
体素子を収容後、キャビティの開口に蓋をするキャップ
を溶接するために、金属のウェルドリング4が、ろう付
けなどによシ接合されておった。
Conventionally, this caged ceramic package for semiconductor devices was
As shown in the cross-sectional view of FIG. 3, a ceramic base 11 has a cavity 2 in the center for fixing a semiconductor element.
A metal weld ring 4 is bonded to the upper surface around the cavity 2 by brazing or the like in order to weld a cap that covers the opening of the cavity after the semiconductor element is housed in the cavity 2. Ta.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置用セラミックパッケージは、
ウェルドリング取付けを行なうときに専用治具が必要で
あυ、また、取付は位置精度を出しにくいという欠点が
ある。
The conventional ceramic package for semiconductor devices mentioned above is
A special jig is required when attaching the weld ring, and there is also the disadvantage that it is difficult to achieve positional accuracy when attaching the weld ring.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

上記問題点に対し、本発明では、セラミック基体の、半
導体素子を収容固着するキャビティ周囲の上面に、この
キャビティに蓋をするだめのキャップヲ浴接するウェル
ドリング位置決め用の凸部または凹部を設けている。
In order to solve the above problems, the present invention provides a convex part or a concave part on the upper surface of the ceramic base around the cavity in which the semiconductor element is housed and fixed, for positioning the weld ring that contacts the cap for covering the cavity. .

〔実施例〕〔Example〕

つぎに本発明を実施例によシ説明する。 Next, the present invention will be explained using examples.

第1図(a)は本発明の一実施例のキャップを除いた平
面図、同図(blは同図(a)のA−A断面図である。
FIG. 1(a) is a plan view of an embodiment of the present invention with the cap removed, and FIG. 1(b) is a cross-sectional view taken along line A-A in FIG.

第1図+a) 、 (b)において、これを第3図に示
した従来例と比べると、セラミック基体1のキャビティ
2の周囲上面に、ウェルドリンク4が接合されているの
は同じであるが、本例においては、四角形のウェルドリ
ンク4の相対向する一対の内側面に沿って、ウェルドリ
ンク4の位置決め用の凸部3が設けられているのが第3
図の従来例と違っている。
In Fig. 1+a) and (b), when comparing this with the conventional example shown in Fig. 3, it is the same that the weld link 4 is joined to the upper surface of the periphery of the cavity 2 of the ceramic base 1. In this example, the third protrusion 3 for positioning the well link 4 is provided along a pair of opposing inner surfaces of the rectangular well link 4.
This is different from the conventional example shown in the figure.

第2図は本発明の他の実施例の断面図であり、本例では
ウェルドリンク4は、セラミック基体5の半導体素子固
着用キャビティ2の周囲上面に設けた凹部6に、丁度は
まることによってウェルドリンク4の位置決めがなされ
ている。
FIG. 2 is a cross-sectional view of another embodiment of the present invention. In this embodiment, the well link 4 fits into the recess 6 provided on the upper surface of the periphery of the semiconductor element fixing cavity 2 of the ceramic base 5. Drink 4 has been positioned.

〔発明の効果〕〔Effect of the invention〕

以上説明したよりに本発明は、セラミック基体の半導体
素子固定のキャビティ周囲上面に1ウェルドリング位置
決め用の凸部または凹部を設けることによシ、ウェルド
リング取付は用専用治具が不要となり、また、ウェルド
リング取付は精度を向上させる効果がある。
As explained above, the present invention provides a convex portion or a concave portion for positioning one weld ring on the upper surface around the cavity for fixing the semiconductor element of the ceramic base, thereby eliminating the need for a special jig for mounting the weld ring, and , weld ring attachment has the effect of improving accuracy.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の一実施例のキャップを除いた平
面図、同図(b)は同図(aJのA−A断面図である。 第2図は本発明の他の実施例のキャップなしの断面図、
第3図は従来のセラミックパッケージのキャップなしの
断面図である。 1.5.11・・・・・・セラミック基体、2・・・・
・・キャビティ、3・・・・・・ウェルドリング位置決
め用凸部。 4・・・・・・ウェルドリング、6・・・・・・位置決
め用凹部。 ゝ−′−一二
FIG. 1(a) is a plan view of one embodiment of the present invention with the cap removed, and FIG. Example cross section without cap,
FIG. 3 is a sectional view of a conventional ceramic package without a cap. 1.5.11...Ceramic base, 2...
...Cavity, 3...Protrusion for positioning the weld ring. 4... Weld ring, 6... Positioning recess.ゝ−′−12

Claims (1)

【特許請求の範囲】[Claims] 金属キャップをシームウエルドにて封止するためのウエ
ルドリングをセラミック基体のキャビティ周囲の上面に
有する半導体装置用セラミックパッケージにおいて、前
記ウエルドリング位置決めのための凸部または凹部を前
記セラミック基体の上面に有することを特徴とする半導
体装置用セラミックパッケージ。
A ceramic package for a semiconductor device having a weld ring on the upper surface around a cavity of a ceramic base for sealing a metal cap with a seam weld, the ceramic base having a protrusion or a recess for positioning the weld ring on the upper surface of the ceramic base. A ceramic package for semiconductor devices characterized by:
JP2533486A 1986-02-06 1986-02-06 Ceramic package for semiconductor device Pending JPS62183146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2533486A JPS62183146A (en) 1986-02-06 1986-02-06 Ceramic package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2533486A JPS62183146A (en) 1986-02-06 1986-02-06 Ceramic package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS62183146A true JPS62183146A (en) 1987-08-11

Family

ID=12163023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2533486A Pending JPS62183146A (en) 1986-02-06 1986-02-06 Ceramic package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS62183146A (en)

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