JPH03203353A - Package of semiconductor device - Google Patents

Abstract

PURPOSE:To relieve the concentration of stress caused by heat applied at the time of packaging, and prevent the generation of cracks in a package by arranging a groove in a glass sealing surface of the package of a semiconductor device. CONSTITUTION:A semiconductor chip 8 is fixed in a recessed part of a package base 1, covered with a cap 2, and sealed with sealing glass 4. In this constitution, a groove 5 for relieving stress is made in the central part of a sealing surface 3 having a width W in the manner in which the groove is aligned to the package base 1 and the cap 2. Thus the sealing surface 3 is divided into an outer region and an inner region by the groove 5, and the area is reduced, so that the stress also becomes one-half. Thereby cracks are hardly generated in the package base 1 and the cap 2.

Description

DETAILED DESCRIPTION OF THE INVENTION C. Industrial Application Field The present invention relates to a package for a semiconductor device, and particularly to a glass-sealed package.

[Conventional technology]

FIG. 3 is a cross-sectional view showing the package and the accommodated semiconductor chip of this type of conventional semiconductor device. In FIG. 3, after a semiconductor chip 8 is fixed in a recess of a package base 1 having a recess in the center for fixing a semiconductor chip, a cap 2 having a peripheral wall like the base 1 is sealed to the sealing surface of the base 1. They were butted together with the sealing glass 4 in between, and the interior was hermetically sealed by welding the sealing glass 4.

[Problem to be solved by the invention]

In the conventional semiconductor device package described above, glass is welded to the entire surface of the butted sealing surface, so the difference in thermal expansion coefficient between the package base, cap, and sealing glass causes large stress on the sealing surface. occurs. Therefore, there is a drawback that the package is likely to crack due to thermal stress when the package is mounted on the board by soldering.

[Means to solve the problem]

In order to solve the above problem, the present invention provides a groove in the abutting sealing surface between the package base and the cap to alleviate stress concentration.

〔Example〕

Next, the present invention will be explained by examples.

FIG. 1(a) is a sectional view showing an embodiment of the present invention and a housed semiconductor chip, and FIG. 1(b) is a plan view of the package base shown in FIG. 1(a). In these figures, we refer to this as the third
Compared to the conventional example shown in the figure, the semiconductor chip is fixed in a recess of a package base 1, covered with a cap 2, and sealed with a sealing glass 4, which is the same. However, in this example, in the sealing surface 3 of the peripheral wall soil surface having a width W, a groove 5 for stress relaxation is provided in both the base body 1 and the cap 2 along the center of the width. This groove 5 divides the glass sealing surface 3 into an outer region and an inner region, and the area of one region is approximately half of that before division, and as this area is reduced, the stress is also halved. It becomes difficult to crack.

FIG. 2 is a plan view of a package base according to a second embodiment of the present invention. In FIG. 2, hook-shaped double inner and outer grooves 6a and 6b are carved in the four corners of the glass sealing surface 3 of the peripheral wall surrounding the rectangular recess. Although not shown, it goes without saying that grooves are also carved in the four corners of the sealing surface of the cap in pairs with the grooves of the base body 1. Since the thermal stress applied to the package tends to concentrate at the four corners, by providing grooves at the four corners of the sealing surface as in this embodiment, the stress at the four corners can be effectively alleviated.

〔Effect of the invention〕

As described above, the present invention has the effect that by providing a groove in the glass sealing surface of a semiconductor device package, stress concentration due to heat applied during mounting can be alleviated, and the package is less likely to crack.

[Brief explanation of drawings]

FIG. 1(a) is a cross-sectional view showing the first embodiment of the present invention and the accommodated semiconductor chip, FIG. 1(b) is a plan view of the package base shown in FIG. 1(a), and FIG. FIG. 3 is a plan view of a package base according to a second embodiment, and a cross-sectional view showing a conventional semiconductor device package and an accommodated semiconductor chip. DESCRIPTION OF SYMBOLS 1...Package base, 2...Cap, 3...Glass sealing surface, 4...Sealing glass, 5, 6a, 6b... ... Stress relaxation groove, 8
・・・・・・Semiconductor chip.

Claims (1)

[Claims] The package has a package base to which a semiconductor chip is fixed, and a cap that covers an opening of the recess after the semiconductor chip is fixed to a recess of the package base, and a glass is provided between the package base and the cap. 1. A glass-sealed semiconductor device package, characterized in that a stress-relaxing groove is provided in a sealing surface of the glass seal.