JPS61124155A - Solder sealing method of semiconductor device - Google Patents
Solder sealing method of semiconductor deviceInfo
- Publication number
- JPS61124155A JPS61124155A JP24440684A JP24440684A JPS61124155A JP S61124155 A JPS61124155 A JP S61124155A JP 24440684 A JP24440684 A JP 24440684A JP 24440684 A JP24440684 A JP 24440684A JP S61124155 A JPS61124155 A JP S61124155A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- sealing
- lid
- package
- fusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007789 sealing Methods 0.000 title claims abstract description 37
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims description 18
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 239000011521 glass Substances 0.000 abstract description 9
- 239000000919 ceramic Substances 0.000 abstract description 7
- 230000004907 flux Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000008602 contraction Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置の半田を用いた封止方法に係り、特
に封止温度が制限（約２００℃以下）される半導体素子
、例えば色フィルタを有する固体撮像素子の封正に好適
な半導体装置の半田封止方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for sealing semiconductor devices using solder, and is particularly applicable to semiconductor devices whose sealing temperature is limited (approximately 200° C. or less), such as color filters. The present invention relates to a method for solder-sealing a semiconductor device suitable for sealing a solid-state image sensor having a semiconductor device.
一般に、半導体装置においては、半導体素子は外気から
の影響を受けないようにリッドとパッケージとを封止し
てその中に密閉されている。Generally, in a semiconductor device, a semiconductor element is hermetically sealed between a lid and a package so as not to be affected by the outside air.
そして、半田封止は主としてメタルリッドとメタライズ
面を有するセラミックペツγ−ジ間で行われている。し
かし、固体撮像素子のように受光用の透明ガラス面のあ
るパッケージ構造におけるガラスリッドを用いた封止の
場合、ガラス材が低弾性であることから、半田が固化す
る時、内部気体が収縮してもガラスが変形しに＜＜、封
止部の半田を内部に吸い込む現壕が生じ、結果として封
止幅の減少及び信頼性の低下を招いていた。The solder sealing is mainly performed between the metal lid and the ceramic peg having a metallized surface. However, in the case of sealing using a glass lid in a package structure with a transparent glass surface for receiving light, such as a solid-state image sensor, the internal gas contracts when the solder solidifies because the glass material has low elasticity. Even when the glass is deformed, a trench is created in which the solder of the sealing portion is sucked into the interior, resulting in a reduction in the sealing width and a decrease in reliability.
従来、半田を用いた封止方法として、例えば特開昭５８
−１８６９５２号公報に示すように、高温ガスを接着部
のろう剤に吹き付は溶着させる方法及び特開昭５８−１
２７４７４号公報に示ｔように、封（６部に介在させた
特殊半田を超音波エネルギーで融解固着させる方法が知
られている。Conventionally, as a sealing method using solder, for example, JP-A-58
As shown in Japanese Patent Publication No. 186952, there is a method of spraying and welding high-temperature gas to the soldering agent at the bonded part, and JP-A-58-1
As shown in Japanese Patent No. 27474, a method is known in which special solder interposed in the seal (6 parts) is melted and fixed using ultrasonic energy.
しかし、前者ではキャビティ内部の気体収縮による封止
幅の問題は解決されず、後者においても封止部全体にわ
たり一定直以上の封市幅を確保するのは困難であり、し
かもワイヤボンディング後の超音波加振はワイヤの共撮
によるワイヤ同志のタッチ不良、断線などの問題が生じ
る。However, the former method does not solve the problem of sealing width due to gas contraction inside the cavity, and the latter method also makes it difficult to secure a sealing width of a certain degree or more over the entire sealing area, and furthermore, Sonic excitation causes problems such as poor touching of the wires and disconnection due to co-photography of the wires.
本発明の目的は、低弾性リッドとパッケージを半田によ
って封止する封止方法において、封止部の半田封止幅の
均一化を図り、信頼性を確保することができる半導体装
置の半田封止方法を提供することにある。An object of the present invention is to provide a solder-sealed semiconductor device that can ensure reliability by making the solder-sealing width of the sealing part uniform in a sealing method that seals a low-elasticity lid and a package with solder. The purpose is to provide a method.
本発明は上記目的を達成するために、封止部の一部に開
口部を形成してリッドとパッケージとを半田で封止し、
その後前記開口部を密封することを特徴とする。In order to achieve the above object, the present invention forms an opening in a part of the sealing part and seals the lid and the package with solder.
The method is characterized in that the opening is then sealed.
以下、本発明の一実施例を第１図乃至第３図により説明
する。第１図に示すように、半導体装置は、リッド１０
と、パッケージ２０と、このパッケージ２０に固着され
た半導体素子３０とからなり、半導体素子３０の電極と
パッケージ２０のリードとはワイヤ３１で接続されてい
る。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. As shown in FIG. 1, the semiconductor device includes a lid 10
It consists of a package 20 and a semiconductor element 30 fixed to the package 20, and the electrodes of the semiconductor element 30 and the leads of the package 20 are connected by wires 31.
前記リッド１０は、第１図及び第２図に示すように、メ
タライズ層１１を持つセラミックリング１２がガラス板
１３にフリットガラス１４で溶着されている。前記メタ
ライズｌ−１１は封止部の全面には設けられてはいなく
、メタライズ処理されていない箇所１５を有する。そし
て、メタライズ層１１にプリフォーミング法によって半
田１６が溶着されている。前記プリフォーミング法は、
封止部分のメタライズ層１１に半田１６を予めフラック
スを用いて溶着させ、その後フラックス洗浄する。この
プリフォーミング時には、メタライズ処理されていない
箇所１５には半田１６が溶着しなく、切欠き部１７が形
成される。As shown in FIGS. 1 and 2, the lid 10 has a ceramic ring 12 having a metallized layer 11 welded to a glass plate 13 with a frit glass 14. The metallization l-11 is not provided on the entire surface of the sealing portion, and has a portion 15 that is not metalized. Then, solder 16 is welded to the metallized layer 11 by a preforming method. The preforming method includes:
Solder 16 is previously welded to the metallized layer 11 in the sealing portion using flux, and then the flux is washed. During this preforming, the solder 16 is not welded to the portions 15 that have not been metallized, and a cutout portion 17 is formed.
前記パッケージ２０は、第１図及び第３図に示すように
、セラミック２１の封止部にメタライズ層２２が設けら
れている。メタライズ層２２は前記リッド１０と同様に
封止部の全面には設けられていなく、リッド１０の切欠
き部１７（第２図（ｂ）参照）に対応した箇所２３はメ
タライズ処理されていない。そして、メタライズ層２２
に前記リッド１０と同様にプリフォーミング法によって
半田２４が溶着されている。従って、このプリフォーミ
ング時には、メタライズ処理されていない箇所２３には
半田２４が溶着しなく、切欠き部２５が形成される。As shown in FIGS. 1 and 3, the package 20 includes a metallized layer 22 in the sealing portion of the ceramic 21. Similar to the lid 10, the metallized layer 22 is not provided on the entire surface of the sealing portion, and a portion 23 corresponding to the notch 17 (see FIG. 2(b)) of the lid 10 is not metalized. Then, the metallized layer 22
As with the lid 10, solder 24 is welded to the lid 10 by a preforming method. Therefore, during this preforming, the solder 24 is not welded to the portions 23 that have not been metallized, and a cutout portion 25 is formed.
次に、リッド１０の切欠き部１７とパッケージ２０の切
欠き部２５が合うように、リッド１０の半田１６の面と
、半導体素子３０が組込まれたパッケージ２０の半田２
４の面を合せ、２００℃程度の封止温度（共晶Ｐｂ−８
ｎ半田の場合）で溶着させる。これζこより第４図に示
す半導体装置が得られる。この場合、リッド１０の切欠
き部１７とパッケージ２０の切欠き部２５とで開口部４
０が形成され、この開口部４０は封止部の溶着時におけ
る内部ガスのガス抜は孔となるので、半田封止幅の均一
性が保証される。次に開口部４０をガラス・セラミック
用半田で圓温にて密封ｒる。Next, the surface of the solder 16 of the lid 10 and the solder 2 of the package 20 in which the semiconductor element 30 is installed are aligned so that the notch 17 of the lid 10 and the notch 25 of the package 20 are aligned.
4 and sealing temperature of about 200℃ (eutectic Pb-8
n solder)). From this ζ, the semiconductor device shown in FIG. 4 is obtained. In this case, the opening 4 is formed by the notch 17 of the lid 10 and the notch 25 of the package 20.
0 is formed, and since this opening 40 serves as a hole for venting the internal gas during welding of the sealing portion, uniformity of the solder sealing width is ensured. Next, the opening 40 is sealed with glass/ceramic solder at a temperature of 100 ℃.
第５図は本発明の他の実施例を示す。セラミック２１の
積層プレートの一部を切欠いて開口部４１を形成し、焼
結などの方法によりセラミック２１を作り、これを用い
てパッケージ２０としてもよい。この場合、リッド１０
は第２図のように切欠き部１７を有しても、有しなくて
もよい。FIG. 5 shows another embodiment of the invention. A part of the laminated plate of the ceramic 21 may be cut out to form an opening 41, and the ceramic 21 may be made by a method such as sintering, and the package 20 may be made using this. In this case, lid 10
may or may not have a notch 17 as shown in FIG.
以上の説明から明らかなように、本発明によれば、リッ
ドとパッケージとの封止部に開口部を有するので、開口
部が内部ガスのガス抜き孔となり、封止部の半田封止幅
が均一化し、信頼性が向上する。特に色フィルタが半導
体素子上に形成され、処理温度に制限のある固体撮像素
子などの機密封止が信頼性を損わずに行える。As is clear from the above description, according to the present invention, since the sealing portion between the lid and the package has an opening, the opening serves as a vent hole for internal gas, and the solder sealing width of the sealing portion is reduced. Uniformity and improved reliability. In particular, color filters are formed on semiconductor elements, and solid-state image sensors and the like, which have limited processing temperatures, can be hermetically sealed without losing reliability.
第１図は本発明ｌこなる半田封止方法の一実施例を示し
、（ａ）は斜視図、（ｂ）は断面図、第２図は第１図の
リッドを示し、＋ａ）はプリフォーミング前の斜、夜回
、（ｂ）はプリフォーミング後の側面図、第３図は第１
図のパッケージを示し、（ａ）はプリフォーミング前の
斜視図、（ｂ）はプリフォーミング後の側面図、第４図
は第２図のリッドと第３図のパッケージとの封止後の斜
視図、第５図は本発明の他の実施例を示すｔ４ツケージ
の斜視図である。
１０ ・リッド、 １６・・・半田、１７・・
・切欠き、 ２０・・・パッケージ、２４・・
・半田、２５・・・切欠き、
４０．４１ ・開口部。
一／ −
第１Ｆ
第２ｔ
（ｂ）
く
（ｂ）
第３
第４図
（ｂ）
第５図1 shows an embodiment of the solder sealing method according to the present invention, (a) is a perspective view, (b) is a sectional view, FIG. 2 is a lid shown in FIG. Oblique view before forming, night view, (b) side view after preforming, Figure 3 shows the first
4 shows a perspective view of the package shown in FIG. 3, where (a) is a perspective view before preforming, (b) is a side view after preforming, and FIG. 4 is a perspective view of the lid shown in FIG. 2 and the package shown in FIG. 3 after being sealed. FIG. 5 is a perspective view of a T4 cage showing another embodiment of the present invention. 10・Lid, 16...Solder, 17...
・Notch, 20...Package, 24...
・Solder, 25...notch, 40.41 ・Opening. 1/ - 1F 2t (b) Ku (b) 3 Figure 4 (b) Figure 5
Claims (1)
導体装置の半田封止方法において、封止部の一部に開口
部を形成して前記リツドと前記パッケージとを半田で封
止し、その後前記開口部を密封することを特徴とする半
導体装置の半田封止方法。In a solder-sealing method for a semiconductor device in which a low-elasticity lid and a package are sealed with solder, an opening is formed in a part of the sealing portion, the lid and the package are sealed with solder, and then the A method for solder-sealing a semiconductor device, characterized by sealing an opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24440684A JPS61124155A (en) | 1984-11-21 | 1984-11-21 | Solder sealing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24440684A JPS61124155A (en) | 1984-11-21 | 1984-11-21 | Solder sealing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61124155A true JPS61124155A (en) | 1986-06-11 |
Family
ID=17118188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24440684A Pending JPS61124155A (en) | 1984-11-21 | 1984-11-21 | Solder sealing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61124155A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016163005A (en) * | 2015-03-05 | 2016-09-05 | セイコーインスツル株式会社 | Component for package, electronic component, and manufacturing method of electronic component |
-
1984
- 1984-11-21 JP JP24440684A patent/JPS61124155A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016163005A (en) * | 2015-03-05 | 2016-09-05 | セイコーインスツル株式会社 | Component for package, electronic component, and manufacturing method of electronic component |
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