JPS62180431A - Detecting circuit for fault of signal processor - Google Patents

Abstract

PURPOSE:To detect the fault of a signal processor with simple circuit constitution by transferring the contents of an internal RAM of the signal processor having an address designated by an address bus to the internal RAM of the (N+1)-th signal processor prepared for detection of faults at the time of N pieces of signal processors are actuated in parallel with each other. CONSTITUTION:An address bus 20 must be set at '0' when the fault of a signal processor 1 is detected. Here only the contents of an internal RAM of the processor 1 are outputted to a bus signal line 90. While signal processors 2-4 output no output of contents of internal RAM. A control terminal 70 is enabled and the delivered RAM contents are written to the internal RAM of a signal processor 5. The signal processor functions to output the same signal with supply of the same input after the same RAM contents are once secured.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a failure detection circuit used when a plurality of signal processors are operated in parallel.

(Prior art) A conventional signal processor receives an input signal, starts processing, and after completing the processing of a unit cycle, simply sets a flag indicating that it can output to notify the outside that the processing has finished. It is.

(Problems to be Solved by the Invention) In the conventional signal processor failure detection circuit described above, it is impossible to see from the outside how the internal processing is progressing, and therefore, multiple signal processors are operated in parallel. The disadvantage is that it is not possible to establish a faulty signal processor when the signal processor is running.

An object of the present invention is to provide a terminal for setting an address, a terminal for connecting an address bus, and an internal RAM in a signal processor, which is a microprocessor for high-speed Ig processing.
When N (N: positive integer) signal processors are operated in parallel, the contents of the internal RAM of the signal processor with the address specified by the address bus will be disabled By transferring the signal to the internal RAM of the (N+1)th signal processor prepared for detection, the above drawback can be removed, and a failure can be detected by making both signal processors perform the same operation and comparing the output signals. The object of the present invention is to provide a signal processor fault detection circuit configured as follows.

(Means for solving the problem) The signal processor failure detection circuit according to the present invention includes N (
a signal processor for signal processing (N: positive integer);
+1)th fault detection signal processor and an exclusive OR gate.

The signal processor for signal processing of Na has a terminal for address setting, a terminal for address bus connection, and an internal R
It is equipped with AM input/output terminals and can perform parallel processing operations.

The (N+1)th failure detection signal processor is Nf
Transfers the contents of the internal RAM of the i-th (N〉i〉1: positive integer) signal processor having the address specified by the address bus among the f61 signal processors, and stores it in the provided internal RAM. It is something that can be done.

The exclusive OR gate is for comparing the outputs obtained when the i-th and (N+1)-th 7-signal processors are made to operate in the same manner.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a signal processor failure detection circuit according to the present invention. In Figure 1,
1 to 5 are signal processors, and 6 is an exclusive OR gate.

In FIG. 1, it is assumed that signal processors 1 to 4 are operating in parallel. Each address setting terminal 30,
40. Enter 0°1.2.8 into SQ and 60, respectively. The signal processor 5 is added for fault detection, and the address bus 20 is input to the address setting terminal.

To detect a failure of signal processor I, address bus 20 must be set to zero. At this time, only the contents of the internal RAM of the signal processor 1 are output to the pass signal H90, and the signal processors 2 to 4 do not output the contents of the internal RAM. The control terminal 70 is enabled and the output RAM contents are transferred to the internal RA of the signal processor 5.
MK rose.

In a signal processor, once the contents of the RAM are made the same, the signal processor operates to output the same signal when the same human power is input.

Therefore, the signal processor S added for fault detection
Input the same signal as signal processor 1 to the signal processor 1, input the outputs on the respective output signals m80 and 100 to the exclusive OR gate 6, and the output signal on the signal -/1M100 corresponds to the output signal of the signal processor l. If the signal processor 1 is all 0, it can be determined that the signal processor 1 is operating normally.

To detect failures in the other signal processors 2 to 4, the address buses 20 may be set to 1.2.8 and similar operations may be performed.

(Effects of the Invention) As explained above, the present invention provides N11i! ] When operating the signal processors in parallel, the contents of the internal RAM of the signal processor with the address specified by the address bus are transferred to the internal RAM of the (N+1)th signal processor, which is prepared for failure detection. Another advantage is that fault detection can be performed with a simple circuit configuration.

Therefore, a fault detection circuit can be easily realized, and a fault can be effectively detected when a signal processor is incorporated into a device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a signal processor failure detection circuit according to the present invention. 1 to 5...Signal processor 6...Exclusive OR gate

Claims (1)

[Claims] N signal processors (N: a positive integer) that are equipped with terminals for address setting, terminals for address bus connection, and internal RAM input/output terminals and can perform parallel processing operations; The first of the signal processors with the address specified by the address bus (
Internal RA of the signal processor (N≧i>1: positive integer)
A (N+1)th signal processor provided for fault detection capable of transferring the contents of M and storing it in a provided internal RAM, and the i-th and (N+1)th signal processors are caused to perform the same operation. 1. A signal processor failure detection circuit comprising: an exclusive OR gate for comparing output signals obtained when