JPS6451535A - Sequence abnormality detection system for interface - Google Patents

Sequence abnormality detection system for interface

Info

Publication number
JPS6451535A
JPS6451535A JP62209095A JP20909587A JPS6451535A JP S6451535 A JPS6451535 A JP S6451535A JP 62209095 A JP62209095 A JP 62209095A JP 20909587 A JP20909587 A JP 20909587A JP S6451535 A JPS6451535 A JP S6451535A
Authority
JP
Japan
Prior art keywords
flip
flop
request signal
signal
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62209095A
Other languages
Japanese (ja)
Inventor
Joichi Futaki
Seiichi Yatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP62209095A priority Critical patent/JPS6451535A/en
Publication of JPS6451535A publication Critical patent/JPS6451535A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To easily locate an abnormal point by providing a monitor unit consisting of a first memory circuit which is set when detecting a request signal and a second memory circuit which resets the first memory circuit by simultaneously detecting a request signal and a response signal and is set on condition that a response signal and a request signal do not exist concurrently. CONSTITUTION:When a request signal is inputted to the monitor unit 4b, the first memory circuit i.e. a flip-flop Q1 is set. And if a response signal to the request signal is inputted, the condition of a NAND circuit B is satisfied, and the flip-flop Q1 is reset. In normal operation, the flip-flop Q1 is immediately reset after being set, and a flip-flop Q2 is not set. In case a request signal is generated in a signal line 3 and stopped by the returning of the response signal, the flip-flop Q1 is not reset by an output from the NAND circuit B, instead, the flip-flop Q2 is set by an output from an AND circuit A. In case both flip-flops Q1, Q2 are set, lamps L1, L2 are turned on via a lamp driver D to display a fault.
JP62209095A 1987-08-21 1987-08-21 Sequence abnormality detection system for interface Pending JPS6451535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62209095A JPS6451535A (en) 1987-08-21 1987-08-21 Sequence abnormality detection system for interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62209095A JPS6451535A (en) 1987-08-21 1987-08-21 Sequence abnormality detection system for interface

Publications (1)

Publication Number Publication Date
JPS6451535A true JPS6451535A (en) 1989-02-27

Family

ID=16567204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62209095A Pending JPS6451535A (en) 1987-08-21 1987-08-21 Sequence abnormality detection system for interface

Country Status (1)

Country Link
JP (1) JPS6451535A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012098932A (en) * 2010-11-02 2012-05-24 Hitachi Ltd Power supply monitoring device and information processing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012098932A (en) * 2010-11-02 2012-05-24 Hitachi Ltd Power supply monitoring device and information processing device

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