JPS62179748A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPS62179748A JPS62179748A JP61023106A JP2310686A JPS62179748A JP S62179748 A JPS62179748 A JP S62179748A JP 61023106 A JP61023106 A JP 61023106A JP 2310686 A JP2310686 A JP 2310686A JP S62179748 A JPS62179748 A JP S62179748A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- sealing
- substrate
- semiconductor element
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 239000000919 ceramic Substances 0.000 claims abstract description 33
- 238000007789 sealing Methods 0.000 claims abstract description 25
- 239000003566 sealing material Substances 0.000 abstract description 18
- 239000000758 substrate Substances 0.000 abstract description 13
- 238000005219 brazing Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 229910001111 Fine metal Inorganic materials 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/16315—Shape
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体素子をセラミック基体に固定し、キャ
ップをかぶせて、ガラスや樹脂などの封止材料で封止す
る半導体装置用パッケージに関する０
〔従来の技術〕
半導体装置の気密封止方法として、ガラス、樹脂等の封
止材料を利用した封止が一般に行われている。従来のセ
ラミックパッケージの半導体装置の製造工程では、第３
図の断面図に示すように。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a package for a semiconductor device in which a semiconductor element is fixed to a ceramic substrate, covered with a cap, and sealed with a sealing material such as glass or resin. [Prior Art] As a method for hermetically sealing a semiconductor device, sealing using a sealing material such as glass or resin is generally performed. In the conventional manufacturing process of semiconductor devices in ceramic packages, the third
As shown in the cross section of the figure.
まず、半導体素子固着部２に固着した半導体素子９と外
部との電気的導通をとるための配線パターン、及び封止
材料４を取シ付けたセラミック基体１を用意する。この
セラミック基体の半導体素子固着部２に電子回路のパタ
ーンを作シ込んだ半導体素子９を接着する。半導体素子
９上の電極とセラミック基体１の電極を１！、Ａｕ等の
細１１１１０で接続することによ）パッケージの外部電
極と半導体素子との電気的導通をとる。次に、封止材料
４を取シ付けたキャップ６をセラミック基体１の上に置
き、荷重を加えて加熱し、封止材料４を溶融させて気密
封止を行なう。封止工程の加熱温度は半導体素子に悪影
響を与えないよう低めに設定されている。このため、セ
ラミック基体とキャップを押し付けるようにクリップ等
で荷重をかけて封止作業を行なっている。次に品名等を
捺印し、外観、電気的特性等の検査を行ない半導体装置
が完成する。First, a ceramic substrate 1 is prepared, on which a wiring pattern for establishing electrical continuity between the semiconductor element 9 fixed to the semiconductor element fixing part 2 and the outside, and a sealing material 4 are attached. A semiconductor element 9 having an electronic circuit pattern printed thereon is adhered to the semiconductor element fixing portion 2 of this ceramic base. The electrode on the semiconductor element 9 and the electrode on the ceramic substrate 1 are 1! , Au, etc.) to establish electrical continuity between the external electrodes of the package and the semiconductor element. Next, the cap 6 to which the sealing material 4 is attached is placed on the ceramic substrate 1, and a load is applied and heated to melt the sealing material 4 and perform airtight sealing. The heating temperature in the sealing process is set low so as not to adversely affect the semiconductor element. For this reason, sealing work is performed by applying a load with a clip or the like to press the ceramic base and the cap together. Next, the product name, etc. is stamped, and the appearance, electrical characteristics, etc. are inspected, and the semiconductor device is completed.
上述した従来のパッケージでは、封止工程の荷重及び溶
融した封止材料の粘度のバラつきによシ、封止状態が変
化してしまう。荷重または溶融が不十分だと、セラミッ
ク基体の封止材料とキャップの封止材料との間に隙間が
あいたままとな夛、気密封止ができない。また、荷重が
強すぎると、封止材料部がつぶれ過ぎてしまう。このた
め封止材料が流れ出し、外観を損なう。また内側に流れ
出すと金属細線を切断してしまうという欠点があった。In the conventional package described above, the sealed state changes due to variations in the load of the sealing process and the viscosity of the melted sealing material. If the loading or melting is insufficient, a gap will remain between the ceramic base sealing material and the cap sealing material, and a hermetic seal will not be achieved. Moreover, if the load is too strong, the sealing material portion will be crushed too much. This causes the sealing material to flow out and spoil the appearance. Another drawback was that if it flowed inward, it would cut the thin metal wire.
本発明の半導体装置用パッケージは、内部に半導体素子
が固定されるセラミック基体にキャップをかぶせて蓋を
し、封止材料で封止するセラミック基体とキャップの接
触面、すなわち、気密封止面にセラミックの突起を設け
ている。In the semiconductor device package of the present invention, a cap is placed over a ceramic base in which a semiconductor element is fixed, and a contact surface between the ceramic base and the cap, which is sealed with a sealing material, that is, an airtight sealing surface is sealed. It has ceramic protrusions.
図を参照して本発明の実施例について説明する。 Embodiments of the present invention will be described with reference to the drawings.
第１図＋ａ）は本発明の第一の実施例に係る半導体装置
のキャップなしの平面図、同図（ｂ）はキャップ付きの
断面図である。これらの図において、半導体素子９がＡ
ｕ／８ｊ等のろう材でセラミック基体１の中央凹所底面
の半導体素子固定部２に固定されている。半導体素子９
の電極とセラミック基体１の内部電極３とを金属細線１
０で接続する。セラミック基体１の内部電極３と外部電
極は電気的に導通しておシ、半導体素子９とセラミック
基体１の外部電極との導通がとられる。セラミック基体
１の周辺のキャップとの封止部の４箇所には、突起５が
設けられてお〕、この突起５を除いた封止面に封止材料
４を取付けたセラミック基体１に、キャップ６を載せ、
荷重および熱を加えて気密封止し、半導体素子９を外気
からしゃ断する。この封止工程では、クリップによシ荷
重を加え、加熱するが、従来のパッケージではクリップ
のはさむ強さのバラつき、加熱温度のバラつきによシ封
止された形状が変化してしまうが、本実施例ではセラミ
ックの突起５を設けたことによシ、封止部に必要な高さ
を確保することができる。したがって封止作業時の荷重
を強めにすることができ、気密封止ができないという不
良が発生する危険性を低減できる。また、キャップ６を
パッケージのセラミック突起部５に接触するまで押し付
けるため封止部の高さを均一にすることができる。この
ため、封止材料の流れ出しによる外観損傷、金属細線の
切断を回避できる。本実施例ではセラミックの突起部を
パッケージ側に取シ付けたが、キャップ側に取シ付けて
も同様の効果が得られる。FIG. 1(a) is a plan view of a semiconductor device according to a first embodiment of the present invention without a cap, and FIG. 1(b) is a sectional view with a cap. In these figures, the semiconductor element 9 is A
It is fixed to the semiconductor element fixing part 2 on the bottom surface of the central recess of the ceramic base 1 with a brazing material such as u/8j. Semiconductor element 9
and the internal electrode 3 of the ceramic base 1 are connected to
Connect with 0. The internal electrode 3 and the external electrode of the ceramic substrate 1 are electrically connected, and the semiconductor element 9 and the external electrode of the ceramic substrate 1 are electrically connected. Projections 5 are provided at four locations around the ceramic base 1 in the sealing portion with the cap.] The cap is attached to the ceramic base 1 with the sealing material 4 attached to the sealing surface excluding the projections 5. Put 6 on it,
The semiconductor element 9 is hermetically sealed by applying a load and heat to cut off the semiconductor element 9 from the outside air. In this sealing process, a load is applied to the clip and it is heated, but in conventional packages, the sealed shape changes due to variations in the clamping strength of the clips and variations in the heating temperature. In the embodiment, by providing the ceramic protrusion 5, the necessary height of the sealing portion can be secured. Therefore, the load during the sealing operation can be increased, and the risk of defects such as failure to achieve airtight sealing can be reduced. Further, since the cap 6 is pressed until it comes into contact with the ceramic protrusion 5 of the package, the height of the sealing portion can be made uniform. Therefore, damage to the appearance and cutting of the thin metal wire due to the flow of the sealing material can be avoided. In this embodiment, the ceramic protrusion is attached to the package side, but the same effect can be obtained by attaching it to the cap side.
第２図は本発明の第二の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
仁の実施例では、セラミック基体１及びキャップ６にそ
れぞれセラミックの突起７と８を設けている。更に、こ
の突起の頂面に拡互いにかみ合う凹凸をつけてあル、封
止作業時、この突起部をかみ合わせることによ）％位置
合わせができるため、第１の実施例に比べ封止作業が容
易で、また、封止の位置精度が向上する。In Jin's embodiment, the ceramic base 1 and the cap 6 are provided with ceramic protrusions 7 and 8, respectively. Furthermore, the top surface of this protrusion is provided with expanding and interlocking unevenness, and during the sealing process, alignment can be achieved by interlocking the protrusions, which makes the sealing process easier than in the first embodiment. In addition, the positional accuracy of sealing is improved.
なお、これらの実施例で、突起部の高さの合計が、封止
材料の厚みと等しいか、それよシ低いことが必要なのは
いうまでもない。It goes without saying that in these embodiments, the total height of the protrusions must be equal to or lower than the thickness of the sealing material.
なお、上記実施例はチップ・キャリアタイプのパッケー
ジについて述べたが、パッケージの形状はこれに限定さ
れず、ＤＩＰタイプ、ＰＧＡタイプ等種々の形状のもの
が考えられる。Although the above embodiment has been described with respect to a chip carrier type package, the shape of the package is not limited to this, and various shapes such as a DIP type and a PGA type can be considered.
以上説明したように、本発明はセラミックパッケージの
封止面にセラミックの突起部を設けることによシ、気密
封止不良の発生を低減できる。また、封止部の高さを均
一にできるため、封止材料の流れ出しによる外観不良、
金属細線の切断を回避できる。As described above, the present invention can reduce the occurrence of hermetic sealing defects by providing a ceramic protrusion on the sealing surface of a ceramic package. In addition, since the height of the sealing part can be made uniform, it is possible to prevent poor appearance due to the sealing material flowing out.
Avoid cutting thin metal wires.
第１図（ａ）は本発明の第一の実施例のパッケージを用
いた半導体装置のキャップなしの平面図、同図（ｂ）は
本発明の第一の実施例のパッケージを用いた半導体装置
の断面図、第２図は本発明の第二の実施例のパッケージ
を用いた半導体装置の断面図、第３図は従来のパッケー
ジを用いた半導体装置の断面図である。
１・・・・セラミック基体、２・・・・・・半導体素子
固定部、３・・・・・・内部電極、４・・・・・・封止
材料、５，７゜８・・・・・・セラミック突起部、６・
・・・・キャップ、９・・・・・・半導体素子、１０・
・・・・金属細線。
第１図
弗２囚FIG. 1(a) is a plan view without a cap of a semiconductor device using the package of the first embodiment of the present invention, and FIG. 1(b) is a plan view of a semiconductor device using the package of the first embodiment of the present invention. 2 is a sectional view of a semiconductor device using a package according to a second embodiment of the present invention, and FIG. 3 is a sectional view of a semiconductor device using a conventional package. DESCRIPTION OF SYMBOLS 1...Ceramic base, 2...Semiconductor element fixing part, 3...Internal electrode, 4...Sealing material, 5,7゜8...・Ceramic protrusion, 6・
... Cap, 9 ... Semiconductor element, 10.
...Thin metal wire. Figure 1 弗2 prisoners
Claims (1)
ミック基体と、このセラミック基体の凹所に蓋をし内部
を気密封止するキャップとを具えた半導体装置用パッケ
ージにおいて、前記気密封止面に突起が設けられている
ことを特徴とする半導体装置用パッケージ。 ２）上記封止面の突起は、セラミック基体とキャップの
両方の互いに突き合うような位置に設けられ、かつ、こ
の突起の頂面は互いにかみ合うような凹と凸に形成され
ていることを特徴とする特許請求の範囲第１項に記載の
半導体装置用パッケージ。[Scope of Claims] 1) A semiconductor device package comprising a ceramic base having a recess in the center to which a semiconductor element is fixed, and a cap that covers the recess of the ceramic base and hermetically seals the inside. A package for a semiconductor device, characterized in that a protrusion is provided on the hermetically sealed surface. 2) The protrusions on the sealing surface are provided at positions where both the ceramic base and the cap abut each other, and the top surfaces of the protrusions are formed in concave and convex shapes so as to engage with each other. A package for a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61023106A JPS62179748A (en) | 1986-02-04 | 1986-02-04 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61023106A JPS62179748A (en) | 1986-02-04 | 1986-02-04 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62179748A true JPS62179748A (en) | 1987-08-06 |
Family
ID=12101214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61023106A Pending JPS62179748A (en) | 1986-02-04 | 1986-02-04 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62179748A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7432590B2 (en) * | 2004-08-11 | 2008-10-07 | Sanyo Electric Co., Ltd | Ceramic package, assembled substrate, and manufacturing method therefor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5849442B2 (en) * | 1978-12-29 | 1983-11-04 | 神鋼電機株式会社 | vibrating conveyor |
-
1986
- 1986-02-04 JP JP61023106A patent/JPS62179748A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5849442B2 (en) * | 1978-12-29 | 1983-11-04 | 神鋼電機株式会社 | vibrating conveyor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7432590B2 (en) * | 2004-08-11 | 2008-10-07 | Sanyo Electric Co., Ltd | Ceramic package, assembled substrate, and manufacturing method therefor |
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