JPH0650991Y2 - Package for storing semiconductor devices - Google Patents

Package for storing semiconductor devices

Info

Publication number
JPH0650991Y2
JPH0650991Y2 JP13376588U JP13376588U JPH0650991Y2 JP H0650991 Y2 JPH0650991 Y2 JP H0650991Y2 JP 13376588 U JP13376588 U JP 13376588U JP 13376588 U JP13376588 U JP 13376588U JP H0650991 Y2 JPH0650991 Y2 JP H0650991Y2
Authority
JP
Japan
Prior art keywords
semiconductor element
insulating
insulating frame
package
insulating base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP13376588U
Other languages
Japanese (ja)
Other versions
JPH0254249U (en
Inventor
公明 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP13376588U priority Critical patent/JPH0650991Y2/en
Publication of JPH0254249U publication Critical patent/JPH0254249U/ja
Application granted granted Critical
Publication of JPH0650991Y2 publication Critical patent/JPH0650991Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【考案の詳細な説明】 (産業上の利用分野) 本考案は半導体素子を収容するための半導体素子収納用
パッケージの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to an improvement of a semiconductor element housing package for housing a semiconductor element.

(従来の技術) 従来、半導体素子、特に半導体集積回路素子を収容する
ための半導体素子収納用パッケージは第3図及び第4図
に示すように、上面中央部に半導体素子が載置取着され
る載置部を有する矩形形状の絶縁基体11と、該絶縁基体
11の半導体素子載置部を囲繞するように中央部に開孔A
を有し、かつ前記絶縁基体11と同一の外形寸法を有する
絶縁枠体12と、内部に収容する半導体素子を外部の電気
回路に電気的に接続するための外部リード端子13とから
構成されており、絶縁基体11の上面に外部リード端子13
及び絶縁枠体12を順次載置させ、夫々を低融点のガラス
14で接着固定することによって製作されている。
2. Description of the Related Art Conventionally, as shown in FIGS. 3 and 4, a semiconductor element housing package for housing a semiconductor element, particularly a semiconductor integrated circuit element, has a semiconductor element mounted and mounted on a central portion of an upper surface thereof. Rectangular insulating substrate 11 having a mounting portion, and the insulating substrate
An opening A is formed in the central part so as to surround 11 semiconductor element mounting parts.
And an insulating frame body 12 having the same outer dimensions as the insulating base body 11, and an external lead terminal 13 for electrically connecting a semiconductor element housed inside to an external electric circuit. The external lead terminal 13 on the upper surface of the insulating substrate 11.
And the insulating frame 12 are placed one after another, and each of them has a low melting point glass.
It is made by bonding and fixing with 14.

かかる従来の半導体素子収納用パッケージはその内部へ
の半導体素子の収容が通常、絶縁枠体12の直交する二側
面を治具に当接させ、絶縁枠体12に設けた開孔Aを所定
位置に固定した後、前記開孔A内に位置する絶縁基体11
の半導体素子載置部に半導体素子15を載置取着させると
ともに半導体素子15の各電極をボンディングワイヤ16を
介して外部リード端子13に接続させ、最後に絶縁枠体12
の上部に該絶縁枠体12の開孔Aを塞ぐように蓋部材17を
低融点のガラスを介し取着することによって行われてお
り、内部に半導体素子を気密に封止することによって最
終製品としての半導体装置となる。
In such a conventional package for housing a semiconductor element, the semiconductor element is usually housed in the package by abutting two orthogonal side surfaces of the insulating frame body 12 with a jig so that the opening A provided in the insulating frame body 12 is located at a predetermined position. After being fixed to the insulating base 11 located in the opening A,
The semiconductor element 15 is mounted and mounted on the semiconductor element mounting portion of the device, each electrode of the semiconductor element 15 is connected to the external lead terminal 13 via the bonding wire 16, and finally the insulating frame 12
The lid member 17 is attached to the upper part of the insulating frame 12 so as to close the opening A of the insulating frame 12 through a glass having a low melting point, and the semiconductor element is hermetically sealed in the final product. As a semiconductor device.

(考案が解決しようとする課題) しかし乍ら、この従来の半導体素子収納用パッケージは
絶縁基体と絶縁枠体との接着がガラスを用いて行われて
いることから絶縁基体11と絶縁枠体12の接着位置にズレ
を生じ易く、絶縁基体11と絶縁枠体12の各々の側面をす
べて同一の平面となるように接着するのが困難で、絶縁
基体11の一部側面が絶縁枠体12の側面より外側に突出し
た状態で接着されたものとなる。そのためこの半導体素
子収納用パッケージに半導体素子を収容する際、絶縁枠
体12の直交する二辺を治具に当接させ、絶縁枠体12に形
成した開孔Aを所定位置に固定する場合、絶縁基体11の
側面が絶縁枠体12の側面より突出していることから絶縁
枠体12の側面を治具に当接させることができなくなり、
その結果、絶縁枠体12に設けた開孔Aを所定位置に固定
するのが不可となって、半導体素子をパッケージの所定
位置に正確に載置取着することができなくなるという欠
点を有していた。
(Problems to be solved by the invention) However, in this conventional semiconductor element housing package, the insulating base 11 and the insulating frame 12 are adhered to each other by using glass. Of the insulating base body 11 and the insulating frame body 12 are difficult to bond so that the side surfaces of the insulating base body 11 and the insulating frame body 12 are all on the same plane. It is bonded so that it protrudes outward from the side surface. Therefore, when a semiconductor element is accommodated in this semiconductor element accommodating package, when two orthogonal sides of the insulating frame body 12 are brought into contact with a jig and the opening A formed in the insulating frame body 12 is fixed at a predetermined position, Since the side surface of the insulating substrate 11 projects from the side surface of the insulating frame body 12, the side surface of the insulating frame body 12 cannot be brought into contact with the jig,
As a result, it becomes impossible to fix the opening A provided in the insulating frame 12 at a predetermined position, and it becomes impossible to accurately mount and mount the semiconductor element at the predetermined position of the package. Was there.

また半導体素子を所定位置に正確に載置取着できないこ
とから該半導体素子の各電極と外部リード端子とを接続
するワイヤボンディングの作業が正確にできないという
欠点も有していた。
Further, since the semiconductor element cannot be accurately placed and mounted at a predetermined position, there is a drawback that the wire bonding work for connecting each electrode of the semiconductor element and the external lead terminal cannot be performed accurately.

(考案の目的) 本考案は上記欠点に鑑み案出されたもので、その目的は
半導体素子を所定位置に正確に載置取着するのを可能と
するとともに半導体素子の各電極と外部リード端子とを
容易、かつ確実に接続することが可能な半導体素子収納
用パッケージを提供することにある。
(Object of the Invention) The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to enable a semiconductor element to be accurately placed and mounted in a predetermined position, and each electrode of the semiconductor element and an external lead terminal. It is an object of the present invention to provide a package for housing a semiconductor element capable of easily and surely connecting to and.

(課題を解決するための手段) 本考案は半導体素子が載置される載置部を有する絶縁基
体と該載置部を囲繞し、内部に半導体素子を収容する空
所を形成するための絶縁枠体とを、その間に外部リード
端子を挟んでガラス付けして成る半導体素子収納用パッ
ケージにおいて、前記絶縁基体の外形寸法を絶縁枠体の
外形寸法より小さくしたことを特徴とするものである。
(Means for Solving the Problem) The present invention provides an insulating substrate having a mounting portion on which a semiconductor element is mounted, and an insulating material surrounding the mounting portion and forming a void for accommodating the semiconductor element therein. A semiconductor element housing package comprising a frame and a glass body with an external lead terminal sandwiched between the frame and the frame, wherein the outer dimensions of the insulating base are smaller than the outer dimensions of the insulating frame.

(実施例) 次に本考案を第1図及び第2図に示す実施例に基づき詳
細に説明する。
(Embodiment) Next, the present invention will be described in detail based on an embodiment shown in FIGS. 1 and 2.

第1図及び第2図は本考案の半導体素子収納用パッケー
ジの一実施例を示し、1はアルミナセラミックス等の電
気絶縁材料より成る絶縁基体、2同じく電気絶縁材料よ
り成る絶縁枠体である。
1 and 2 show an embodiment of a package for accommodating a semiconductor device of the present invention, 1 is an insulating base made of an electrically insulating material such as alumina ceramics, and 2 is an insulating frame made of an electrically insulating material.

前記絶縁基体1はその上面中央部に半導体素子を載置取
着するための載置部を有しており、該載置部には半導体
素子3がガラス、樹脂等の接着材を介し取着固定され
る。
The insulating substrate 1 has a mounting portion for mounting and mounting a semiconductor element on the center of the upper surface thereof, and the semiconductor element 3 is mounted on the mounting portion via an adhesive material such as glass or resin. Fixed.

前記絶縁基体1は、従来周知のプレス成形法を採用する
ことによって形成され、例えば絶縁基体1がアルミナセ
ラミックスより成る場合には、図に示すような矩形形状
の絶縁基体に対応した形状を有するプレス型内にアルミ
ナセラミックスの粉末を充填させるとともに一定圧力を
印加して成形し、しかる後、これを役1500℃の温度で焼
成することによって製作される。
The insulating base 1 is formed by adopting a conventionally known press molding method. For example, when the insulating base 1 is made of alumina ceramics, a press having a shape corresponding to a rectangular insulating base as shown in the drawing is used. It is manufactured by filling alumina ceramic powder in a mold and applying a constant pressure to mold it, and then firing it at a temperature of 1500 ° C.

また前記絶縁基体1の上面には外部リード端子4を間に
挟んで絶縁枠体2がガラス5を介し接着されている。
Further, an insulating frame body 2 is adhered to the upper surface of the insulating substrate 1 with a glass 5 sandwiching an external lead terminal 4 therebetween.

前記絶縁枠体2はその中央部に開孔Bが形成されてお
り、絶縁基体1の半導体素子が載置取着される載置部を
囲繞するような枠状の形状となっている。この絶縁枠体
2はその中央部の開孔Bと絶縁基体1上面とで半導体素
子3を内部に収容するための空所を形成する。
The insulating frame 2 has an opening B formed in the center thereof, and has a frame-like shape surrounding a mounting portion on which the semiconductor element of the insulating base 1 is mounted and mounted. The insulating frame 2 has a hole B at the center thereof and the upper surface of the insulating substrate 1 to form a space for accommodating the semiconductor element 3 therein.

前記絶縁枠体2はアルミナセラミックス等の電気絶縁材
料より成り、前述の絶縁基体1と同様の方法によって製
作され、絶縁基体1の上面に、例えば低融点のガラス5
によって接着固定される。
The insulating frame body 2 is made of an electrically insulating material such as alumina ceramics, and is manufactured by the same method as the insulating base body 1 described above.
Fixed by adhesion.

また前記絶縁基体1と絶縁枠体2との間に配される外部
リード端子4はコバール(Fe-Ni-Co合金)や42Alloy(F
e-Ni合金)等の金属から成り、該外部リード端子4は半
導体素子3の各電極がボンディングワイヤ6を介し電気
的に接続され、外部リード端子4を外部回路と接続する
ことにより半導体素子3が外部回路と接続されることと
なる。
The external lead terminals 4 arranged between the insulating substrate 1 and the insulating frame 2 are made of Kovar (Fe-Ni-Co alloy) or 42Alloy (F
The external lead terminal 4 is electrically connected to each electrode of the semiconductor element 3 through a bonding wire 6, and the external lead terminal 4 is connected to an external circuit to connect the external lead terminal 4 to an external circuit. Will be connected to an external circuit.

前記外部リード端子4は絶縁基体1と絶縁枠体2とをガ
ラス5を介し接着する際、同時に両者の間に接着固定さ
れる。
When the insulating substrate 1 and the insulating frame body 2 are bonded via the glass 5, the external lead terminals 4 are simultaneously bonded and fixed between the two.

尚、前記絶縁基体1と絶縁枠体2との接着は、絶縁基体
1上面及び絶縁枠体2下面の夫々に予めガラス5の粉末
を塗布しておき、絶縁基体1の上面に外部リード端子4
及び絶縁枠体2を順次載置させた後、加熱し、絶縁基体
1と絶縁枠体2に予め塗布させておいたガラス粉末を溶
融させ、一体化させることによって行われる。
In order to bond the insulating base body 1 and the insulating frame body 2, powder of glass 5 is applied to the upper surface of the insulating base body 1 and the lower surface of the insulating frame body 2 in advance, and the external lead terminals 4 are attached to the upper surface of the insulating base body 1.
Then, the insulating frame body 2 is sequentially placed and then heated to melt the glass powder previously applied to the insulating base body 1 and the insulating frame body 2 to integrate them.

かくして、この半導体素子収納用パッケージによれば、
絶縁基体1の半導体素子載置部に半導体素子3を接着材
を介し取着するとともに該半導体素子3の各電極をボン
ディングワイヤ6を介し外部リード端子4に電気的に接
続した後、絶縁枠体2の上面に蓋部材7をガラス、樹脂
等で接着させ、内部に半導体素子3を気密に封止するこ
とによって最終製品としての半導体装置となる。
Thus, according to this semiconductor element housing package,
After the semiconductor element 3 is attached to the semiconductor element mounting portion of the insulating substrate 1 via an adhesive and each electrode of the semiconductor element 3 is electrically connected to the external lead terminal 4 via the bonding wire 6, the insulating frame is formed. The lid member 7 is adhered to the upper surface of the glass member 2 with glass, resin, or the like, and the semiconductor element 3 is hermetically sealed inside to form a semiconductor device as a final product.

本考案においては絶縁基体の外形寸法を絶縁枠体の外形
寸法より小さくしておくことが重要である。このため第
1図及び第2図に示す実施例では、例えば絶縁基体1を
プレス成形法を採用して製作する際のプレス型の内径を
絶縁枠体2を製作するプレス型の内径より小にしておく
ことによって絶縁基体1の外形寸法を絶縁枠体2の外形
寸法より小となるように形成されている。このように絶
縁基体1の外形寸法を絶縁枠体2の外形寸法より小とな
るようにしておくと、絶縁基体1上に絶縁枠体2をガラ
ス5を用いて接着した場合、絶縁基体1と絶縁枠体2と
の間に位置ズレを生じたとしても絶縁基体1の側面一部
が絶縁枠体2の側面より突出することはない。従ってこ
の半導体素子収納用パッケージに半導体素子を収容する
際、絶縁枠体2の直交する二辺を治具に確実に当接させ
て該絶縁枠体2に形成した開孔Bを所定位置に固定する
ことができ、絶縁枠体2の開孔B内に位置する絶縁基体
1の半導体素子載置部に半導体素子を正確に載置取着す
ることができる。
In the present invention, it is important to make the outer dimensions of the insulating base smaller than the outer dimensions of the insulating frame. Therefore, in the embodiment shown in FIGS. 1 and 2, for example, the inner diameter of the press die when the insulating substrate 1 is manufactured by the press molding method is set to be smaller than the inner diameter of the press die for manufacturing the insulating frame body 2. By so doing, the outer dimensions of the insulating base 1 are formed to be smaller than the outer dimensions of the insulating frame 2. If the outer dimensions of the insulating base 1 are smaller than the outer dimensions of the insulating frame 2 in this manner, when the insulating frame 2 is bonded to the insulating base 1 using the glass 5, Even if a positional deviation occurs with the insulating frame body 2, a part of the side surface of the insulating base body 1 does not protrude from the side surface of the insulating frame body 2. Therefore, when a semiconductor element is accommodated in this semiconductor element accommodating package, the two orthogonal sides of the insulating frame 2 are surely brought into contact with the jig to fix the opening B formed in the insulating frame 2 at a predetermined position. Therefore, the semiconductor element can be accurately mounted and mounted on the semiconductor element mounting portion of the insulating base 1 located inside the opening B of the insulating frame 2.

また半導体素子を所定位置に正確に載置取着できること
から該半導体素子の各電極と外部リード端子との接続を
自動ワイヤボンダーを使用して行うことができ、半導体
素子3の各電極を所定の外部リード端子4に正確、且つ
確実に接続させることも可能となる。
Further, since the semiconductor element can be accurately placed and attached at a predetermined position, the connection between each electrode of the semiconductor element and the external lead terminal can be performed using an automatic wire bonder, and each electrode of the semiconductor element 3 can be provided at a predetermined position. It is also possible to connect to the external lead terminal 4 accurately and surely.

尚、前記絶縁基体1の外形寸法、即ち絶縁基体1の長さ
X1、幅Y1は絶縁枠体2の長さX2、幅Y2に対し、X2≧X1
0.2mm、Y2≧Y1+0.2mmとしておくと絶縁基体1と絶縁枠
体2とをガラス5を介し接着する際、両者に位置ズレが
生じたとしても絶縁基体1の側面が絶縁枠体2の側面よ
り外側に突出することは一切なく、半導体素子収納用パ
ッケージの位置決めを完全として半導体素子を半導体素
子収納用パッケージの所定位置に正確に載置取着するこ
とが可能となる。従って絶縁基体1の長さX1、幅Y1は絶
縁枠体2の長さX2、幅Y2に対し、、X2≧X1+0.2mm、Y2
≧Y1+0.2mmとしておくことが好ましい。
The outer dimensions of the insulating base 1, that is, the length of the insulating base 1.
X 1 and width Y 1 are the length X 2 and width Y 2 of the insulating frame 2 , X 2 ≧ X 1 +
When 0.2 mm and Y 2 ≧ Y 1 +0.2 mm are set, when the insulating base 1 and the insulating frame 2 are bonded to each other through the glass 5, even if a positional deviation occurs between the two, the side surface of the insulating base 1 is the insulating frame. It does not project outward from the side surface of the semiconductor device 2 at all, and the semiconductor element housing package can be completely positioned and the semiconductor element can be accurately placed and mounted in a predetermined position of the semiconductor element housing package. Therefore, the length X 1 and the width Y 1 of the insulating base 1 are X 2 ≧ X 1 +0.2 mm, Y 2 with respect to the length X 2 and the width Y 2 of the insulating frame body 2.
It is preferable to set ≧ Y 1 +0.2 mm.

また絶縁基体1の長さX1、幅Y1が絶縁枠体2の長さX2
幅Y2に対し、X2>X1+1.0mm、Y2>Y1+1.0mmとなると絶
縁基体1と絶縁枠体2とをガラス5を用いて接着する
際、その接着面積が小となり、該接着部において内部に
収容する半導体素子の気密封止が破れ易くなることから
絶縁基体1の長さX1、幅Y1は絶縁枠体2の長さX2、幅Y2
に対し、X2≦X1+1.0mm、Y2≦Y1+1.0mmとしておくこと
が望ましい。
The length X 1 of the insulating base 1, the length X 2 of the width Y 1 is an insulating frame member 2,
When X 2 > X 1 +1.0 mm and Y 2 > Y 1 +1.0 mm with respect to the width Y 2 , when the insulating substrate 1 and the insulating frame 2 are bonded together using the glass 5, the bonding area becomes small. The length X 1 and the width Y 1 of the insulating base body 1 are the length X 2 and the width Y 2 of the insulating frame body 2 because the airtight sealing of the semiconductor element housed inside is easily broken at the adhesive portion.
On the other hand, it is desirable to set X 2 ≤X 1 +1.0 mm and Y 2 ≤Y 1 +1.0 mm.

(考案の効果) 本考案の半導体素子収納用パッケージによれば、絶縁基
体の外形寸法を絶縁枠体の外形寸法より小さくしたこと
から絶縁基体上に絶縁枠体をガラスを用いて接着する
際、絶縁基体と絶縁枠体との間に位置ズレが生じたとし
ても絶縁基体の側面一部が絶縁枠体の側面より突出する
ことはない。そのためこの半導体素子収納用パッケージ
に半導体素子を収容する場合、絶縁枠体の直交する二辺
を治具に確実に当接させて該絶縁枠体に形成した開孔を
所定位置に固定することができ、その結果、絶縁枠体の
開孔内に位置する絶縁基体の半導体素子載置部に半導体
素子を正確に載置取着することができる。
(Effect of the Invention) According to the package for housing a semiconductor device of the present invention, since the outer dimension of the insulating base is smaller than the outer dimension of the insulating frame, when the insulating frame is bonded onto the insulating base using glass, Even if the insulating base body and the insulating frame body are misaligned, a part of the side surface of the insulating base body does not protrude from the side surface of the insulating frame body. Therefore, when a semiconductor element is accommodated in this semiconductor element accommodating package, it is possible to make sure that the two orthogonal sides of the insulating frame are brought into contact with the jig to fix the opening formed in the insulating frame at a predetermined position. As a result, the semiconductor element can be accurately mounted and mounted on the semiconductor element mounting portion of the insulating substrate located in the opening of the insulating frame.

また半導体素子を所定位置に正確に載置取着できること
から該半導体素子の各電極と外部リード端子との接続を
自動ワイヤボンダーを使用して行うことができ、半導体
素子の各電極を所定の外部リード端子に正確、且つ確実
に接続させることも可能となる。
Further, since the semiconductor element can be accurately placed and mounted in a predetermined position, each electrode of the semiconductor element and the external lead terminal can be connected using an automatic wire bonder, and each electrode of the semiconductor element can be connected to a predetermined external portion. It is also possible to connect the lead terminals accurately and surely.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案の半導体素子収納用パッケージの一実施
例を示す平面図、第2図は第1図のパッケージの側面
図、第3図は従来の半導体素子収納用パッケージの平面
図、第4図は第3図に示すパッケージの側面図である。 1:絶縁基体、2:絶縁枠体 4:外部リード端子、5:ガラス
FIG. 1 is a plan view showing an embodiment of a semiconductor device housing package of the present invention, FIG. 2 is a side view of the package of FIG. 1, and FIG. 3 is a plan view of a conventional semiconductor device housing package. FIG. 4 is a side view of the package shown in FIG. 1: Insulating substrate, 2: Insulating frame 4: External lead terminal, 5: Glass

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】半導体素子が載置される載置部を有する絶
縁基体と該載置部を囲繞し、内部に半導体素子を収容す
る空所を形成するための絶縁枠体とを、その間に外部リ
ード端子を挟んでガラス付けして成る半導体素子収納用
パッケージにおいて、前記絶縁基体の外形寸法を絶縁枠
体の外形寸法より小さくしたことを特徴とする半導体素
子収納用パッケージ。
1. An insulating substrate having a mounting portion on which a semiconductor element is mounted, and an insulating frame surrounding the mounting portion and forming a space for accommodating the semiconductor element therein. A package for storing a semiconductor element, comprising an external lead terminal sandwiched between glass pieces, wherein the insulating substrate has an outer dimension smaller than that of an insulating frame.
JP13376588U 1988-10-13 1988-10-13 Package for storing semiconductor devices Expired - Lifetime JPH0650991Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13376588U JPH0650991Y2 (en) 1988-10-13 1988-10-13 Package for storing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13376588U JPH0650991Y2 (en) 1988-10-13 1988-10-13 Package for storing semiconductor devices

Publications (2)

Publication Number Publication Date
JPH0254249U JPH0254249U (en) 1990-04-19
JPH0650991Y2 true JPH0650991Y2 (en) 1994-12-21

Family

ID=31391929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13376588U Expired - Lifetime JPH0650991Y2 (en) 1988-10-13 1988-10-13 Package for storing semiconductor devices

Country Status (1)

Country Link
JP (1) JPH0650991Y2 (en)

Also Published As

Publication number Publication date
JPH0254249U (en) 1990-04-19

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