JPS62178544U - - Google Patents
Info
- Publication number
- JPS62178544U JPS62178544U JP6664386U JP6664386U JPS62178544U JP S62178544 U JPS62178544 U JP S62178544U JP 6664386 U JP6664386 U JP 6664386U JP 6664386 U JP6664386 U JP 6664386U JP S62178544 U JPS62178544 U JP S62178544U
- Authority
- JP
- Japan
- Prior art keywords
- island
- lead portions
- recess
- semiconductor
- outer periphery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 2
- 230000035515 penetration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図から第５図までは本考案の実施例を示し
、第１図はリードフレームの平面図、第２図は第
１実施例の要部の平面図、第３図は第２図の―
線視断面図、第４図は第２実施例の要部の断面
図、第５図は第３実施例の要部の断面図、第６図
から第８図は従来技術を示し、第６図は従来のリ
ードフレームの平面図、第７図は要部平面図、第
８図は第７図の―視断面図である。
１，２０……リードフレーム、２……枠体、３
……タイバー、４，２１……半導体チツプ、７，
７ａ，２３……リード部、５，２２……アイラン
ド、６，２５……プリフオーム材、１０……アー
スランド、９，２４……ワイヤ、１１……貫通部
、１２，１３……凹所、１４……パツケージ本体
。
1 to 5 show embodiments of the present invention, FIG. 1 is a plan view of the lead frame, FIG. 2 is a plan view of the main parts of the first embodiment, and FIG. ―
4 is a sectional view of the main part of the second embodiment, FIG. 5 is a sectional view of the main part of the third embodiment, FIGS. 6 to 8 show the prior art, and FIG. 7 is a plan view of a conventional lead frame, FIG. 7 is a plan view of a main part, and FIG. 8 is a sectional view taken along the line shown in FIG. 7. 1, 20...Lead frame, 2...Frame body, 3
...Tie bar, 4,21...Semiconductor chip, 7,
7a, 23... Lead part, 5, 22... Island, 6, 25... Preform material, 10... Earth land, 9, 24... Wire, 11... Penetration part, 12, 13... Recess, 14...Package body.
Claims (1)
ンデイングするアイランドの外周に、複数のリー
ド部を互いに適宜隔て配置し、該各リード部の先
端が前記アイランドの外周縁に対して適宜隔てて
臨むように形成して成る半導体用リードフレーム
において、前記アイランドの外周寄り位置には、
アイランド上面より凹む凹所または貫通部を設け
、該凹所または貫通部を隔てて外側寄りのアイラ
ンドには、前記リード部のうちの任意のリード部
に対してアースのワイヤボンデイングをするため
のアースランドを形成したことを特徴とする半導
体用リードフレーム。 A plurality of lead portions are arranged at appropriate distances from each other on the outer periphery of an island on which a semiconductor chip is die-bonded via a preform material, and the tips of the respective lead portions are formed so as to face the outer periphery of the island at an appropriate distance. In a semiconductor lead frame consisting of
A recess or a penetrating portion recessed from the top surface of the island is provided, and an island located on the outside across the recess or penetrating portion is provided with a ground wire for bonding a ground wire to any one of the lead portions. A semiconductor lead frame characterized by having a land formed therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6664386U JPS62178544U (en) | 1986-04-30 | 1986-04-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6664386U JPS62178544U (en) | 1986-04-30 | 1986-04-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62178544U true JPS62178544U (en) | 1987-11-12 |
Family
ID=30904840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6664386U Pending JPS62178544U (en) | 1986-04-30 | 1986-04-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62178544U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5596666A (en) * | 1979-01-18 | 1980-07-23 | Mitsubishi Electric Corp | Method of fabricating semiconductor device substrate |
| JPS5632459B2 (en) * | 1979-05-31 | 1981-07-28 |
-
1986
- 1986-04-30 JP JP6664386U patent/JPS62178544U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5596666A (en) * | 1979-01-18 | 1980-07-23 | Mitsubishi Electric Corp | Method of fabricating semiconductor device substrate |
| JPS5632459B2 (en) * | 1979-05-31 | 1981-07-28 |