JPS62177934A - Mounting method for semiconductor device - Google Patents
Mounting method for semiconductor deviceInfo
- Publication number
- JPS62177934A JPS62177934A JP61019328A JP1932886A JPS62177934A JP S62177934 A JPS62177934 A JP S62177934A JP 61019328 A JP61019328 A JP 61019328A JP 1932886 A JP1932886 A JP 1932886A JP S62177934 A JPS62177934 A JP S62177934A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- insulating sheet
- solder
- metals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims description 18
- 229910000679 solder Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract 2
- 230000008018 melting Effects 0.000 claims abstract 2
- 239000010953 base metal Substances 0.000 claims description 12
- 150000002739 metals Chemical class 0.000 abstract 5
- 238000007747 plating Methods 0.000 description 9
- 238000004806 packaging method and process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000470 constituent Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は多数の電極を有する半導体装置のICチップを
高密度に実装する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for packaging IC chips of a semiconductor device having a large number of electrodes at high density.
半導体装置内のICチップの実装方法として従来ワイヤ
ボンディングしてパッケージに収容するものや、7リツ
プチツプのように素子表面に設けた突起電極と基板面と
を対向させてワイヤを用いずに接続するフェースダウノ
ボ/ディングなどが知られている。これらの実装方法に
ついて、さらに高密度実装を行うために、例えばワイヤ
ボンディングでは電極パッドの間隔を狭くすると、ワイ
ヤ同志が互に接触してしまうなどの不都合が起きるので
、信頼性の向上、ボンディング工数の低減などの点から
バンプ電極を形成したフリップチップ方式も多用される
ようになっている。Conventional methods for mounting IC chips in semiconductor devices include wire bonding and accommodating them in packages, and face mounting methods such as 7-lip chips, in which protruding electrodes provided on the element surface and the substrate surface face each other and are connected without using wires. Daunobo/Ding etc. are known. Regarding these mounting methods, in order to achieve higher density mounting, for example, in wire bonding, if the spacing between electrode pads is narrowed, inconveniences such as wires touching each other occur, so it is necessary to improve reliability and reduce bonding man-hours. A flip-chip method in which bump electrodes are formed has also come to be widely used in order to reduce the amount of damage.
例えば第3図はフリップチップのバンプ電極を形成する
工程のみを示した模型的断面図であシ、その他の製造工
程は省略しである。第3図(a)においてこの素子は必
要な導電影領域を有するシリコン基板1上に酸化膜(S
i20)2と配線金R(AA)3を形成し、さらにその
上に窒化膜(SisNn) 4を形成して窓明けした後
、下地金属としてTi5とCu6を必要な個所に蒸着し
、Cu6の上にレジスト7をメッキマスクとしてNiメ
ッキ8を施し、次いではんだメッキ9を行った過程であ
る。For example, FIG. 3 is a schematic cross-sectional view showing only the process of forming bump electrodes of a flip chip, and other manufacturing processes are omitted. In FIG. 3(a), this device is constructed by disposing an oxide film (S) on a silicon substrate 1 having a necessary conductive shadow area.
After forming a nitride film (SisNn) 4 on it and opening a window, Ti5 and Cu6 are deposited as base metals at the required locations, and Cu6 is formed. This is a process in which Ni plating 8 was applied on top using resist 7 as a plating mask, and then solder plating 9 was applied.
第3図(b)は引き続きレジスト7の除去、 Ti5の
エツチング後、熱処理してはんだメッキ9をリフローさ
せて半球状の突起電極9aを形成した過程を示している
。第3図(a)から第3図中)K至る過程かられかるよ
うに、突起電極9aを形成するためのはんだメッキ9の
外径寸法は、はんだの凝固の際の収縮分を見越して突起
電極9aの外径寸法よりかなり大きくして置かなければ
ならない。例えば突起電極9aの外径寸法を160μm
、高さを100μmとした場合はんだメッキ9の外径寸
法は260μmを必要とする。このように7リツプチツ
プの場合も高密度実装をするためには突起電極を形成す
る過程で寸法的な制約によって限界があることおよび突
起電極形成の工数が多く歩溜りが悪いなどの欠点をもっ
ている。FIG. 3(b) shows the process of subsequently removing the resist 7 and etching the Ti5, followed by heat treatment to reflow the solder plating 9 to form a hemispherical protruding electrode 9a. As can be seen from the process from FIG. 3(a) to K in FIG. It must be placed much larger than the outer diameter of the electrode 9a. For example, the outer diameter of the protruding electrode 9a is 160 μm.
When the height is 100 μm, the outer diameter of the solder plating 9 is required to be 260 μm. As described above, the 7-lip chip also has drawbacks such as there are limitations due to dimensional constraints in the process of forming the protruding electrodes in order to achieve high-density packaging, and the number of steps required to form the protruding electrodes is large, resulting in poor yields.
したがってフリップチップのような突起電極を有する半
導体装置の製造効率を高めより高密度な実装を可能とす
る方法が望まれる。Therefore, a method is desired that increases the manufacturing efficiency of semiconductor devices having protruding electrodes such as flip chips and enables higher density packaging.
本発明は上述の点に鑑みてなされたものであり、その目
的はフリップチップの突起電極の形成が容易であり、し
かも高密度実装が可能な方法を提供することにある。The present invention has been made in view of the above-mentioned points, and an object thereof is to provide a method that facilitates the formation of protruding electrodes of a flip chip and allows high-density packaging.
本発明はフリップチップにはじめから突起電極を形成す
ることなく、別途電極部を設けた絶縁シートを用意し、
この絶縁シートを半導体素子と基板との間に配置し、絶
縁シートの電極部が半導体素子の下地金属と基板の導電
パターンとにそれぞれ位置決めされるようにして半導体
素子と基板をボンディングすることにより、突起電極形
成過程における電極数の制約や製造水溜りの低下などの
ない高密度実装を可能にしたものである。The present invention does not require forming protruding electrodes on the flip chip from the beginning, but instead prepares an insulating sheet with a separate electrode section.
By placing this insulating sheet between the semiconductor element and the substrate, and bonding the semiconductor element and the substrate so that the electrode portions of the insulating sheet are positioned respectively on the underlying metal of the semiconductor element and the conductive pattern of the substrate, This enables high-density mounting without restrictions on the number of electrodes in the process of forming protruding electrodes and without reducing production water retention.
以下本発明を実施例に基づき説明する。 The present invention will be explained below based on examples.
第1図は本発明が適用される半導体装置の分解断面図で
ある。第1図Aの10は半導体素子、11はその上に設
けられた例えばTi 、 Cu 、 Ni々どを堆積し
た下地金属である。第1図Bの12は例えばポリイミド
フィルムなどの絶縁シートである。絶縁シート12には
下地金属11に対応する位置に例えばNi13などの金
属を埋め込んだ後、絶縁シート12を溶融はんだ中に浸
漬して金属Nt13の上下両表面にのみ表面張力による
半球状のはんだ14を設けである。第1図Cはセラミッ
クなどの基板15の上にAg −Pdなどの導電パター
ン16が下地金属11と対応する位置に被着されたもの
である。FIG. 1 is an exploded sectional view of a semiconductor device to which the present invention is applied. In FIG. 1A, 10 is a semiconductor element, and 11 is a base metal on which, for example, Ti, Cu, Ni, etc. are deposited. 12 in FIG. 1B is an insulating sheet such as a polyimide film. After embedding a metal such as Ni 13 in the insulating sheet 12 at a position corresponding to the base metal 11, the insulating sheet 12 is immersed in molten solder, and hemispherical solder 14 is applied only to the upper and lower surfaces of the metal Nt 13 by surface tension. This is provided. In FIG. 1C, a conductive pattern 16 made of Ag-Pd or the like is deposited on a substrate 15 made of ceramic or the like at a position corresponding to the base metal 11. In FIG.
以上のごとくあらかじめ作製した下地金属11をもった
半導体素子10.金@Ni13の両端面に半球状のけん
だ14を備えた絶縁シート12および導電パターン16
の形成された基板15を、この順に重ねて加熱炉を通す
とけんだ14が溶融し、この個所で位置合わせされてい
る下地金属11と導電パターン16とがそれぞれはんだ
接合され、絶縁シート12は半導体素子10と基板15
との間に挾まれて金JiiNi13を介して固定される
。Semiconductor element 10 with base metal 11 prepared in advance as described above. Insulating sheet 12 and conductive pattern 16 with hemispherical solders 14 on both end faces of gold@Ni 13
When the substrates 15 on which are formed are stacked in this order and passed through a heating furnace, the solder 14 melts, the base metal 11 and the conductive pattern 16 aligned at this point are soldered together, and the insulating sheet 12 is Semiconductor element 10 and substrate 15
It is sandwiched between and fixed via gold JiiNi 13.
第2図はこのようKして実装された半導体装置の断面図
を示したものであり、第1図と共通部分を同一符号で表
わしである。第2図かられかるように本発明の方法は電
極部となる金属をもった絶縁シート12をスペーサーと
して用い、これを半導体素子10と基板15の間に介在
するようにしてボンディングしてhるので、7リツプチ
ツプにおける一括ボンディングが可能であり、しかもこ
れら半導体装置の構成部材をそれぞれ別個に作製するこ
とができ、従来のワイヤボンディングの長所であるボン
ディング材が半導体素子から離れているという利点をも
兼ね備え、電極の外径寸法は半導体素子10に設ける下
地金[11の大きさによって決定されるから、電極密変
が増し高密度実装が可能となる。また従来の7リツプチ
ツプの突起電極に相当するものは安価な絶縁シート12
の方に簡単に形成することができるので突起電極を形成
するための歩溜りもよく、実装工数も低減され経済的に
有利な半導体装置が得られる。また電極部の構成材料を
備えたシートはポリイミドフィルムなどを用いるときは
巻き取ることができるから、テープキャリアなどのよう
Kしてボンディングを自動化することも可能であり、さ
らに工数の低減が期待される。FIG. 2 shows a cross-sectional view of a semiconductor device mounted in this way, and parts common to those in FIG. 1 are denoted by the same reference numerals. As can be seen from FIG. 2, the method of the present invention uses as a spacer an insulating sheet 12 containing metal, which will serve as an electrode portion, and bonding the semiconductor element 10 and the substrate 15 so that this sheet is interposed between the semiconductor element 10 and the substrate 15. Therefore, it is possible to perform batch bonding on 7-lip chips, and the constituent members of these semiconductor devices can be manufactured separately, which also has the advantage of conventional wire bonding in that the bonding material is separated from the semiconductor element. In addition, since the outer diameter of the electrode is determined by the size of the base metal [11] provided on the semiconductor element 10, the electrode density is increased and high-density packaging is possible. In addition, the protruding electrodes of the conventional 7-lip chip are equivalent to the inexpensive insulating sheet 12.
Since the protruding electrodes can be easily formed, the yield for forming the protruding electrodes is good, the number of mounting steps is reduced, and an economically advantageous semiconductor device can be obtained. In addition, since the sheet containing the constituent material of the electrode part can be rolled up when using polyimide film, etc., it is also possible to automate the bonding by using it as a tape carrier, etc., which is expected to further reduce the number of man-hours. Ru.
7リツプチツプボンディングを行なうに当って、従来突
起電極の下地金属より面積の大きいはんだメッキを施し
ておかねばならなかったので、電極の径や電極間距離な
どに関連して電極密度に制約を受け、実装密度ははんだ
メッキの外径寸法によって決められてしまうという問題
があったのに対して、本発明は実施例で説明したように
、半導体素子と基板とは別に、上下両面まで貫通するN
iとその端面に突起はんだを備えた絶縁シートを用意し
、実装に際しては、この絶縁シートを半導体素子と基板
との間に挾み突起はんだを溶融凝固させて、半導体素子
の下地金属と基板の導電パターンとを接合するようにし
たため、電極の外径寸法ははじめから半導体素子上の下
地金属とほぼ同程度となっているから、電極密度に対す
る制約が生じることなくより高密度実装が可能となる。7 When performing lip chip bonding, it was necessary to apply solder plating that had a larger area than the base metal of conventional protruding electrodes, so there were restrictions on electrode density due to factors such as electrode diameter and distance between electrodes. However, as explained in the embodiment, the present invention has a problem in that the mounting density is determined by the outer diameter of the solder plating.However, as explained in the embodiment, the present invention has a solder plate that penetrates both the top and bottom sides separately from the semiconductor element and the board. N
An insulating sheet with solder protrusions on the end face of the i is prepared, and during mounting, this insulating sheet is sandwiched between the semiconductor element and the substrate, the solder protrusions are melted and solidified, and the base metal of the semiconductor element and the substrate are bonded. Since the electrode is bonded to the conductive pattern, the outer diameter of the electrode is almost the same as the underlying metal on the semiconductor element from the beginning, making it possible to implement higher-density mounting without restrictions on electrode density. .
またあらかじめ半導体素子に突起電極を設けることなく
、絶縁シートを半導体素子と基板間に介在させて多数の
電極を同時にボンディングすることができるので、製造
工数が低減され歩溜シも向上するという利点も有するも
のである。In addition, many electrodes can be bonded simultaneously by interposing an insulating sheet between the semiconductor element and the substrate without providing protruding electrodes on the semiconductor element in advance, which has the advantage of reducing manufacturing man-hours and improving yield. It is something that you have.
第1図は本発明が適用される半導体装置の分解断面図、
第2図は本発明により実装された半導体装置の断面図、
第3図は従来の突起電極形成過程を示す半導体素子の断
面図である。
5・・・’rt、6・・・cu、8・・・Niメッキ、
9・・・はんだメッキ、10・・・半導体素子、11・
・・下地金属、12・・・絶縁シート、13・・・金属
Ni、14・・・半球状はんだ、15・・・基板、16
・・・導電パターン。
第1図FIG. 1 is an exploded sectional view of a semiconductor device to which the present invention is applied;
FIG. 2 is a cross-sectional view of a semiconductor device mounted according to the present invention;
FIG. 3 is a cross-sectional view of a semiconductor device showing a conventional process of forming protruding electrodes. 5...'rt, 6...cu, 8...Ni plating,
9...Solder plating, 10...Semiconductor element, 11.
...Base metal, 12...Insulating sheet, 13...Metal Ni, 14...Semispherical solder, 15...Substrate, 16
...conductive pattern. Figure 1
Claims (1)
金属と基板上に形成された導電パターンとを一括ボンデ
ィングするに当り、前記下地金属と前記導電パターンと
の位置合わせ可能な突起電極を上下両面に備えた絶縁シ
ートを前記半導体素子と前記基板の間に挾み、前記突起
電極を溶融凝固させることを特徴とする半導体装置の実
装方法。 2)特許請求の範囲第1項記載の方法において、突起電
極は絶縁シート中を上下表面まで貫通して埋込んだ金属
の両端面上に形成したはんだであることを特徴とする半
導体装置の実装方法。[Claims] 1) When collectively bonding a large number of electrode base metals provided on the main surface of a semiconductor element and a conductive pattern formed on a substrate, the position of the base metal and the conductive pattern is determined. A method for mounting a semiconductor device, comprising sandwiching an insulating sheet having protruding electrodes on both upper and lower surfaces that can be matched together between the semiconductor element and the substrate, and melting and solidifying the protruding electrodes. 2) In the method according to claim 1, the protruding electrodes are solder formed on both end surfaces of metal embedded through the insulating sheet to the upper and lower surfaces. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61019328A JPS62177934A (en) | 1986-01-31 | 1986-01-31 | Mounting method for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61019328A JPS62177934A (en) | 1986-01-31 | 1986-01-31 | Mounting method for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62177934A true JPS62177934A (en) | 1987-08-04 |
Family
ID=11996341
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61019328A Pending JPS62177934A (en) | 1986-01-31 | 1986-01-31 | Mounting method for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62177934A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01155633A (en) * | 1987-12-14 | 1989-06-19 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-01-31 JP JP61019328A patent/JPS62177934A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01155633A (en) * | 1987-12-14 | 1989-06-19 | Hitachi Ltd | Semiconductor device |
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