JPS6217223U - - Google Patents
Info
- Publication number
- JPS6217223U JPS6217223U JP10836885U JP10836885U JPS6217223U JP S6217223 U JPS6217223 U JP S6217223U JP 10836885 U JP10836885 U JP 10836885U JP 10836885 U JP10836885 U JP 10836885U JP S6217223 U JPS6217223 U JP S6217223U
- Authority
- JP
- Japan
- Prior art keywords
- effect transistor
- field effect
- drain
- whose
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 claims 10
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
- Amplifiers (AREA)
Description
第１図はこの考案の第１の実施例の回路構成を
示す接続図、第２図はこの考案の第２の実施例の
回路構成を示す接続図、第３図は従来のモノリシ
ツク増幅器の構成を示す接続図である。
１…信号入力端子、２…ソース接地ＦＥＴ、３
…ゲートバイアスおよび入力整合抵抗、４…ゲー
ト接地ＦＥＴ、６…ドレイン負荷素子、７…電源
端子、８…ドレイン接地ＦＥＴ、９…信号出力端
子、１１…定電流源用ＦＥＴ、１３…信号源、１
７…制御信号入力端子、１８…制御信号源、１９
…高周波短絡用容量素子、２１…高周波阻止用抵
抗素子、２２…高周波阻止用インダクタ。
Figure 1 is a connection diagram showing the circuit configuration of the first embodiment of this invention, Figure 2 is a connection diagram showing the circuit configuration of the second embodiment of this invention, and Figure 3 is the configuration of a conventional monolithic amplifier. FIG. 1...Signal input terminal, 2...Source grounding FET, 3
...Gate bias and input matching resistance, 4...Gate grounding FET, 6...Drain load element, 7...Power supply terminal, 8...Drain grounding FET, 9...Signal output terminal, 11...FET for constant current source, 13...Signal source, 1
7... Control signal input terminal, 18... Control signal source, 19
...Capacitive element for high frequency short circuit, 21... Resistance element for high frequency blocking, 22... Inductor for high frequency blocking.
Claims (1)
地された第１の電界効果トランジスタと、 ソースが上記第１の電界トランジスタのドレイ
ンに接続され、ゲートが電界効果トランジスタを
オン状態かオフ状態に設定する制御信号を入力す
る制御信号入力端子に接続され、ドレインが直流
的に電圧を降下し、交流的に負荷となる第１の素
子を介して電源端子に接続された第２の電界効果
トランジスタと、 ゲートが上記第２の電界効果トランジスタのド
レインに接続され、ドレインが上記電源端子に接
続され、ソースが信号出力端子と接続された第３
の電界効果トランジスタと、 ドレインが上記第３の電界効果トランジスタの
ソースと接続され、ゲートが直流的に開放となり
高周波的に短絡となる第２の素子を介して上記第
１の電界効果トランジスタのドレンと接続され、
かつ直流的に短絡となり高周波的に開放となる第
３の素子を介して上記制御信号入力端子に接続さ
れ、ソースが上記第１の電界効果トランジスタの
ドレインと接続された第４の電界効果トランジス
タとから構成されている電界効果トランジスタ増
幅器。[Claims for Utility Model Registration] A first field effect transistor whose gate is connected to a signal input terminal and whose source is grounded; and a field effect transistor whose source is connected to the drain of the first field transistor and whose gate is grounded. It is connected to a control signal input terminal that inputs a control signal to set the on state or off state, and the drain drops the voltage in a DC manner, and is connected to the power supply terminal via the first element that becomes an AC load. a second field effect transistor; and a third field effect transistor, the gate of which is connected to the drain of the second field effect transistor, the drain of which is connected to the power supply terminal, and the source of which is connected to the signal output terminal.
and a drain of the first field effect transistor via a second element whose drain is connected to the source of the third field effect transistor and whose gate is open in terms of DC and short-circuited in terms of high frequency. connected with
and a fourth field effect transistor, which is connected to the control signal input terminal via a third element that is short-circuited in terms of DC and open in terms of high frequency, and whose source is connected to the drain of the first field-effect transistor. A field effect transistor amplifier consisting of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10836885U JPH0418250Y2 (en) | 1985-07-15 | 1985-07-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10836885U JPH0418250Y2 (en) | 1985-07-15 | 1985-07-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6217223U true JPS6217223U (en) | 1987-02-02 |
| JPH0418250Y2 JPH0418250Y2 (en) | 1992-04-23 |
Family
ID=30985500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10836885U Expired JPH0418250Y2 (en) | 1985-07-15 | 1985-07-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0418250Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5040421B2 (en) * | 2007-05-07 | 2012-10-03 | 富士通セミコンダクター株式会社 | Constant voltage circuit, constant voltage supply system, and constant voltage supply method |
-
1985
- 1985-07-15 JP JP10836885U patent/JPH0418250Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0418250Y2 (en) | 1992-04-23 |
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