JP5040421B2 - Constant voltage circuit, constant voltage supply system, and constant voltage supply method - Google Patents

Description

  The present invention relates to a constant voltage output, and more particularly to a constant voltage circuit, a constant voltage supply system, and a constant voltage supply method in which transient voltage fluctuations accompanying fluctuations in input voltage are suppressed.

  With the development of integrated circuit technology, in highly integrated integrated circuits represented by SOC and the like on which a large number of functions are mounted on one chip, miniaturization of elements has progressed and the applied voltage has been lowered due to restrictions on element breakdown voltage. ing. Due to the limitation of the withstand voltage, it is required that there is no transient overshoot of the voltage value. Furthermore, a stable voltage value is also required to ensure high-speed operation. In general, the applied voltage is supplied by converting an external supply voltage supplied from the outside into an internal voltage having a stable constant voltage value.

  A circuit example conventionally proposed as a voltage conversion circuit that converts an external supply voltage into an internal voltage is a circuit that uses a bandgap reference circuit. The band gap reference circuit determines a current by applying a voltage corresponding to the area ratio of a transistor (channel width (W) / channel length (L) in a MOS transistor) to a resistance element having a predetermined resistance value, and is supplied externally. A highly accurate internal voltage can be easily obtained using the voltage as the power supply voltage.

  A specific example is shown in FIG. The case where a MOS transistor is used is illustrated. Current mirror circuits Q1 and Q3 that pass an equivalent current to a pair of MOS transistors Q2 and Q4 having a current mirror circuit configuration, and a MOS transistor Q6 that is a feedback circuit that feeds back a target current are provided. A capacitive element CC is provided between the gate and drain terminals of the MOS transistor Q6 as a countermeasure against oscillation.

  Non-patent document 1 is disclosed as the related technology.

Phillip E. Allen, Douglas R. Holberg, "CMOS ANALOG Circuit Design" (USA), 2nd edition, Oxford UNIVERSITY PRESS, 2002 , P. 425

  In the voltage conversion circuit using the band gap reference circuit which is the circuit example of the background art, it is possible to ensure the accuracy of the output voltage.

  However, when the external supply voltage (power supply voltage) input to the band gap reference circuit suddenly fluctuates, the capacitive element CC connected between the gate and drain terminals of the MOS transistor Q6 provided as an oscillation countermeasure is charged / discharged. Thus, a predetermined time is required until the voltage between the terminals converges to a voltage value corresponding to the power supply voltage. During this time, the circuit state becomes unstable and an overvoltage may occur in the output voltage. The occurrence of overvoltage may cause dielectric breakdown of the element depending on the breakdown voltage of the subsequent circuit, and is also a problem from the viewpoint of element reliability. In particular, in recent high-integrated integrated circuits, when the bias current is set to a small current value, the charge / discharge to the capacitor element CC dominates the circuit operation, so that a significant overvoltage occurs. It is possible that this is a problem.

  The present invention has been made in view of the background art described above, and by providing a low-pass filter circuit in the voltage conversion path from the input voltage to the output voltage, transient voltage fluctuations accompanying fluctuations in the input voltage are suppressed. An object of the present invention is to provide a constant voltage circuit, a constant voltage supply system, and a constant voltage supply method capable of outputting a stable constant voltage.

In order to achieve the above object, a constant voltage circuit according to the present invention is a constant voltage circuit in which an input voltage signal is input to a base terminal or a gate terminal, and a bias current is supplied to the emitter terminal or the source terminal of the input transistor. A current source , a capacitive element having one end connected to the path from the constant current source to the emitter terminal or source terminal of the input transistor, and an emitter that outputs a constant voltage by inputting a voltage signal generated at one end of the capacitive element Or a source follower circuit.

  The constant voltage supply system according to the present invention is a constant voltage supply system that supplies a predetermined voltage to a subsequent circuit, and includes a voltage supply unit that supplies an input voltage signal, and an input voltage signal to a base terminal or a gate terminal. An input transistor, a constant current source for supplying a bias current to the emitter terminal or the source terminal of the input transistor, a capacitor element having one end connected to a path connecting the input transistor and the constant current source, and a capacitor An emitter or a source follower circuit that receives a voltage signal generated at one end of the element and supplies a constant voltage to a subsequent circuit is provided.

  In the constant voltage circuit and the constant voltage supply system according to the present invention, the input voltage signal input to the base terminal or gate terminal of the input transistor is biased by the constant current source to flow through the emitter terminal or source terminal of the input transistor. Depending on the current, it is converted into a voltage value level-shifted by the conduction control voltage of the transistor element at the emitter terminal or the source terminal. Here, the conduction control voltage is a gate-source voltage when a drain current flows in a MOS transistor, and a base-emitter voltage when a collector current flows in a bipolar transistor. Directional voltage. The converted voltage is output from the emitter or source follower circuit via the capacitive element.

  In the signal path from the input voltage signal to the emitter or source follower circuit, a low-pass filter is constituted by the impedance of the input transistor and the capacitive element.

  When the input transistor is a P-type transistor such as a PNP bipolar transistor or a PMOS transistor, a bias current flows from the constant current source to the emitter terminal or the source terminal of the input transistor. In this case, a voltage signal obtained by adding a conduction control voltage to the input voltage signal is input to the emitter or source follower circuit. When the input voltage signal fluctuates to an excessive voltage value, the impedance value becomes high, and the filter effect by the low-pass filter is remarkably exhibited, so that overshoot of the output voltage can be prevented.

  In addition, when the input transistor is an N-type transistor such as an NPN bipolar transistor or an NMOS transistor, a bias current flows out from the emitter terminal or the source terminal of the input transistor toward the constant current source. In this case, a voltage signal obtained by subtracting the conduction control voltage from the input voltage signal is input to the emitter or source follower circuit. When the input voltage signal fluctuates to an undervoltage value, the impedance value becomes high, and the filter effect by the low-pass filter is remarkably exhibited, so that an undershoot of the output voltage can be prevented.

  In a circuit configuration that obtains the output voltage by converting the level of the input voltage signal using the conduction control voltage of the input transistor, the signal propagation of the input voltage signal is achieved by adding a simple circuit element such as a capacitive element to the input of the emitter or source follower circuit. A low pass filter can be inserted in the path. The output voltage can be maintained at a constant voltage by suppressing the transient voltage fluctuation of the input voltage signal.

The constant voltage supply method according to the present invention includes a step of inputting an input voltage signal to the base terminal or gate terminal of the input transistor, and a step of supplying a bias current from the constant current source to the emitter terminal or source terminal of the input transistor. And a step of converting the level of the input voltage signal according to the conduction control voltage of the input transistor by the bias current and outputting the voltage signal from the emitter terminal or the source terminal, and from the constant current source to the emitter terminal or the source terminal of the input transistor. one end path is connected by capacitive element other end to the power supply voltage or a ground voltage is connected, and outputs a step of applying a low pass filter characteristic, a voltage from the emitter follower circuit or a source follower circuit a voltage signal as an input And a step .

In the constant voltage supply method according to the present invention, an input voltage signal is input to the base terminal or the gate terminal of the input transistor. A bias current flows from the constant current source to the emitter terminal or the source terminal of the input transistor. The bias current, the input voltage signal level converted by the voltage signal from the emitter terminal or source terminal in response to the conduction control voltage of the input transistor Ru is output. At this time, a low-pass filter characteristic is given to the signal path.

  As a result, a low-pass filter is constituted by the impedance of the input transistor and the capacitance of the capacitive element in the signal path from the input voltage signal to the emitter or source follower circuit. Filtering sudden fluctuations in the input voltage signal allows the output voltage to be a stable constant voltage.

  When the input transistor is a P-type transistor such as a PNP bipolar transistor or a PMOS transistor, a bias current flows from the constant current source to the emitter terminal or the source terminal of the input transistor. In this case, a voltage signal obtained by adding a conduction control voltage to the input voltage signal is input to the emitter or source follower circuit. When the input voltage signal fluctuates to an excessive voltage value, the impedance value becomes high, and the filter effect is remarkably exhibited, so that overshoot of the output voltage can be prevented.

  In addition, when the input transistor is an N-type transistor such as an NPN bipolar transistor or an NMOS transistor, a bias current flows out from the emitter terminal or the source terminal of the input transistor toward the constant current source. In this case, a voltage signal obtained by subtracting the conduction control voltage from the input voltage signal is input to the emitter or source follower circuit. When the input voltage signal fluctuates to an undervoltage value, the impedance value becomes high, and a filter effect is remarkably exhibited, thereby preventing an undershoot of the output voltage.

  According to the present invention, by adopting a configuration that provides a filter effect in the voltage conversion path from the input voltage to the output voltage, transient voltage fluctuations accompanying fluctuations in the input voltage are suppressed, and a stable constant voltage is output. It is possible to provide a constant voltage circuit, a constant voltage supply system, and a constant voltage supply method that are capable of performing the above.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a constant voltage circuit, a constant voltage supply system, and a constant voltage supply method according to the present invention will be described below in detail with reference to the drawings based on FIGS. In the following description, a case where MOS transistors are used as transistors and diodes is illustrated.

  FIG. 1 shows the principle of the present invention. The voltage conversion unit 1 includes an input terminal A and an output terminal VOUT. The voltage supply unit VIN is connected to the input terminal A, and the input voltage signal VIN is input. The post-stage circuit 2 is connected to the output terminal VOUT.

  The configuration of the voltage conversion unit 1 will be described. The PMOS transistor M1, whose gate terminal is connected to the input terminal A, has a drain terminal connected to the ground voltage GND, and forms a current path between the source terminal and one end of the constant current source IS. Here, the other end of the constant current source IS is connected to the power supply voltage VDD.

  Also, one end of the constant current source IS is connected to the gate terminal of the NMOS transistor M2 constituting the source follower circuit, and the capacitive element C1 is connected to the ground voltage GND. A point X in FIG. 1 is a connection point. The drain terminal of the NMOS transistor M2 is connected to the power supply voltage VDD, and the source terminal is connected to the output terminal VOUT. In addition, the capacitive element C2 is connected between the output terminal VOUT and the ground voltage GND.

  It is conceivable that the diode part D is inserted between the PMOS transistor M1 and the connection point X in addition to the direct connection. The diode part D has a configuration in which diodes D1 to Dn are connected in series in multiple stages. Each of the diodes D1 to Dn is configured by an NMOS transistor having a drain terminal and a gate terminal connected to each other.

The input voltage signal VIN input to the input terminal A is added with the gate-source voltage VGS of the PMOS transistor M1 when the bias current I1 supplied by the constant current source IS flows into the source terminal of the PMOS transistor M1. The level is converted and output to the source terminal. Further, when the diode portion D is provided, the forward voltage is added and the level is converted according to the number of diode stages, and the voltage whose voltage level is shifted up is output to the connection point X. In FIG. 1, since a diode-connected NMOS transistor is used as the diode, the forward voltage of the diode is the gate-source voltage VGS of the NMOS transistor. When there are n stages of diodes, together with the PMOS transistor M1, the voltage signal VX at the connection point X is
VX = VIN + (n + 1) · VGS
It becomes.

The voltage signal VX at the connection point is input to the gate terminal of the NMOS transistor M2. Since the NMOS transistor M2 forms a source follower circuit, the output voltage VOUT output to the output terminal VOUT connected to the source terminal is
VOUT = VIN + n · VGS
It becomes.

  Here, the influence on the output voltage VOUT when the input voltage signal VIN output from the voltage supply unit VIN rises transiently will be considered.

  As the input voltage signal VIN rises, the PMOS transistor M1 is biased in a direction approaching the cutoff state. That is, according to the square characteristic of the drain current ID with respect to the gate-source voltage VGS of the MOS transistor, the drain current ID decreases as the gate-source voltage decreases, making it difficult for the current to flow. The drain current impedance (ΔVGS / ΔID) with respect to the source-to-source voltage VGS increases. In addition, the square characteristics of the MOS transistors are similarly applied to the diodes D1 to Dn constituting the diode part D, so that the forward current decreases and the impedance increases also in the diodes D1 to Dn.

  Since the current flowing from the diode part D through the PMOS transistor M1 is limited, the remainder of the bias current I1 output from the constant current source IS flows to the capacitive element C1, and the capacitive element C1 is charged. By selecting the relationship between the transient rise time of the input voltage signal VIN, the current value of the bias current I1, and the capacitance value of the capacitive element C1, the voltage rise of the voltage signal VX at the connection point X can be suppressed to a slight level. .

  It can be considered that a low-pass filter is provided in the propagation path of the voltage signal from the input terminal A to the connection point X. This is because the NMOS transistor M1 and the impedances of the diodes D1 to Dn and the capacitive element C1 are connected in series. As a result, the propagation of steep fluctuations is blocked by the low-pass filter with respect to the transient rise of the input voltage signal VIN input to the input terminal A.

For example, if the bias current I1 is limited to 10 nA due to a demand for power saving in a highly integrated circuit, and the transient rise time of the input voltage signal VIN is 10 μsec, the capacitance value of the capacitive element C1 can be set to 1 pF. For example, from the equation of t = C1 · ΔVX / I1, which is the relationship with the voltage signal VX at the connection point X,
ΔVX = t · I1 / C1 = 10 (μsec) · 10 (nA) / 1 (pF) = 0.1V. In the transient rise time of the input voltage signal VIN of 10 μsec, the fluctuation range (ΔVX) of the voltage signal X at the connection point X can be suppressed to about 0.1V. That is, the fluctuation range of the output voltage VOUT can be pushed to about 0.1V.

  As a result, the capacitance value of the capacitive element C1 required for suppressing the propagation of the transient voltage rise of the input voltage signal VIN to the output voltage VOUT is equal to the transient rise time of the input voltage signal VIN and the bias current I1. Accordingly, it can be seen that a minute capacitance value of about picofarad (pF) is sufficient. In particular, in a highly integrated integrated circuit, when the bias current I1 is set to a small current value due to the demand for low current consumption, the capacitance value of the capacitive element C1 can be made small, and the integrated circuit has a special value. The capacitive element C1 can be added without providing an arrangement region.

  In the constant voltage circuit that includes the PMOS transistor M1 and outputs the level of the input voltage signal VIN, the low-pass filter can be configured together with the impedance of the PMOS transistor by providing the capacitance element C1 having a small size. The fluctuation of the output voltage VOUT can be suppressed by interrupting the transient voltage rise of the signal VIN.

  In this case, if the diode portion D is provided between the PMOS transistor M1 and the connection point X, the impedance between the input terminal A and the connection point X can be further increased, and the low-pass filter characteristic is further enhanced. Thus, fluctuations in the output voltage VOUT can be suppressed.

  Here, the capacitive element C2 connected between the output terminal VOUT and the ground voltage GND is effective when the input voltage signal VIN transiently decreases. In this case, the PMOS transistor M1 does not approach the cutoff state, and the low-pass filter formed by the PMOS transistor M1 and the capacitive element C1 does not function. However, if the capacitive element C2 is present, the output voltage VOUT is set to a predetermined voltage value. This is because it can be maintained.

  Note that the voltage conversion unit 1, or the voltage conversion unit 1 and the voltage supply unit VIN correspond to the constant voltage circuit of the present application. The voltage conversion unit 1 and the voltage supply unit VIN correspond to the constant voltage supply system of the present application.

  The principle diagram of FIG. 1 illustrates the case where the voltage VGS between the gate and source terminals of the PMOS transistor M1 is added to the input voltage signal VIN, and the output voltage VOUT is constant even when the input voltage signal VIN rises transiently. The case where the voltage is maintained has been described.

  However, the present application is not limited to this. The voltage VGS between the gate and source terminals of the MOS transistor is subtracted from the input voltage signal VIN, and the output voltage VOUT is reduced even when the input voltage signal VIN is transiently decreased. Can be configured to maintain a constant voltage.

  An NMOS transistor is used in place of the PMOS transistor M1, and a voltage signal VX at the connection point X is input by connecting a constant current source so that a bias current flows out from the source terminal of the NMOS transistor instead of the constant current source IS. A voltage value obtained by subtracting VGS from the voltage signal VIN can be used.

  FIG. 2 is a circuit diagram of the embodiment. Portions corresponding to the principle diagram of FIG. 1 are denoted by the same reference numerals as those of the principle diagram, and further description of the configuration is omitted. In the embodiment, the case where there is no diode portion D in the principle diagram of FIG. 1 is illustrated. In the embodiment of FIG. 2, a band gap reference circuit is used as the voltage supply unit VIN.

  The band gap reference circuit VIN has a circuit configuration similar to that of the band gap reference circuit shown in the background art of FIG.

  PMOS transistors Q1 and Q3 constituting a current mirror circuit for supplying an equivalent current are connected to a pair of NMOS transistors Q2 and Q4 having a current mirror circuit configuration. In addition, an NMOS transistor Q6 constituting a feedback circuit for applying feedback via the PMOS transistor Q5 is provided so that this current value becomes the target current. The PMOS transistor Q5 forms a current mirror circuit together with the PMOS transistors Q1 and Q3. A capacitive element CC is provided between the gate and drain terminals of the NMOS transistor Q6 as a countermeasure against oscillation. The current mirror circuit composed of the PMOS transistors Q1 and Q3 further includes a PMOS transistor Q7. The PMOS transistor Q7 is connected to the ground voltage GND via the resistor element R2 and the diode-connected NMOS transistor Q8, and the connection point between the PMOS transistor Q7 and the resistor element R2 is the output terminal of the bandgap reference circuit VIN. This is the input terminal A of FIG.

  The PMOS transistor Q9 is included in a current mirror circuit composed of PMOS transistors Q1, Q3, Q5, and Q7. Of the NMOS transistors Q10 and Q14 constituting the current mirror circuit, the NMOS transistor Q10 is connected to a diode-connected NMOS transistor Q10. The NMOS transistor Q14 is connected to the output terminal VOUT.

  In this circuit configuration, the capacitive element CC provided as a countermeasure for oscillation of the NMOS transistor Q6 constituting the feedback circuit is charged / discharged when the power supply voltage fluctuates, because the voltage between the terminals fluctuates with the fluctuation of the power supply voltage. Is called. When the current value output from the current mirror circuit is small, charging / discharging requires a predetermined time. During this period, the voltage between the terminals of the capacitive element CC is in a transient state and becomes unstable. As a result, the output terminal (terminal A) of the bandgap reference circuit VIN may rise transiently and an overvoltage may occur.

  In the embodiment, since this overvoltage is applied to the terminal A and input to the voltage conversion unit 1 shown in FIG. 1, the voltage is not applied to the terminal A or the voltage does not fluctuate the output voltage VOUT. The output voltage VOUT can be maintained at a constant voltage even with a transient voltage fluctuation at VIN.

  Originally, the bandgap reference voltage VIN is maintained by the transient response in the bandgap reference circuit while maintaining the output voltage VOUT at a constant voltage with high accuracy using the bandgap reference circuit that has little temperature dependence and excellent voltage accuracy. Even when the voltage transiently becomes an overvoltage, the output voltage VOUT can be maintained at a constant voltage.

  In recent integrated circuits, logic circuits that do not require a high-speed response may be integrated, such as a sensor that detects an abnormal state and a real-time clock used for a clock function mounted on a digital device. Such a logic circuit is required not only to operate at high speed, but also to be able to back up for a long time with a battery, a capacitor, or the like due to low current consumption, and thus requires extremely low current consumption. Further, along with miniaturization due to high integration, the breakdown voltage of elements constituting these circuits must be low, and there is a risk of destruction due to application of overvoltage.

  In the present invention, as described above, since the bias current I1 is a small current, the low-pass filter characteristic can sufficiently function. That is, when the band gap reference voltage becomes an overvoltage, the current flowing through the PMOS transistor M1 is limited, and a larger proportion of the bias current I1 output from the constant current source IS flows into the capacitive element C1. However, since the bias current I1 is a small current, the voltage fluctuation at the connection point X accompanying the charging operation to the capacitive element C1 is limited to a small one.

  In a highly integrated circuit, an applied voltage is supplied from the constant voltage circuit according to the embodiment to a circuit that is configured with a low-breakdown-sized microelement and requires a low current consumption such as a sensor or a real-time clock. It is preferable. As a result, in a circuit configuration in which the voltage level is shifted by the conduction control voltage of the transistor element using a voltage with good voltage accuracy such as a band gap reference circuit as an input voltage signal, a signal corresponding to the input voltage signal can be obtained simply by adding a capacitor element. A low-pass filter effect can be given to the propagation path. While maintaining the output voltage at a constant voltage with high accuracy, it is possible to maintain the constant voltage against transient fluctuations in the input voltage signal, and to avoid the situation of overvoltage application to the subsequent circuit.

  In this case, by providing the diode part D shown in FIG. 1, the output voltage VOUT can be maintained at a constant voltage even for a long-term transient fluctuation of the bandgap reference voltage.

  Since the capacitive element C2 is provided between the output terminal VOUT and the ground voltage GND, the output voltage VOUT can be maintained at a constant voltage when the bandgap reference voltage decreases transiently.

  As described above in detail, according to the constant voltage circuit, the constant voltage supply system, and the constant voltage supply method according to the present embodiment, the signal from the input voltage signal VIN to the NMOS transistor M2 which is an example of the emitter or source follower circuit In the path, a low-pass filter is configured by the impedance of the PMOS transistor M1, which is an example of the input transistor, and the capacitive element C1.

  As a result, the bias current I1 flows from the constant current source IS to the source terminal of the PMOS transistor M1. The voltage signal VX obtained by adding the gate-source voltage VGS of the PMOS transistor M1, which is an example of the conduction control voltage, to the input voltage signal VIN is input to the gate terminal of the NMOS transistor M2. When the input voltage signal VIN transiently fluctuates to an excessive voltage value, a filter effect is exerted to prevent the output voltage VOUT from overshooting and can be maintained at a low voltage.

  In this case, if the diode part D is further provided between the PMOS transistor M1 and the connection point X, the impedance of the signal path from the input voltage signal VIN to the NMOS transistor M2 becomes a larger value, and the output voltage is more reliably determined. VOUT can be maintained at a low voltage.

  In applications where low current consumption is required, when the bias current I1 is set to a small current value, the capacitance value of the capacitive element C1 can be set to a capacitance value of about picofarad (pF). In the integrated circuit, the occupation area occupied by the capacitive element C1 can be made small, and it is not necessary to secure a dedicated occupation area.

  The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.

  For example, in the present embodiment, the case where a MOS transistor is used as a constituent element has been described. However, the present invention is not limited to this, and can be realized by a bipolar transistor or a circuit configuration including both a MOS transistor and a bipolar transistor. Needless to say, it can be done.

  The diode portion D has been described by taking a diode-connected MOS transistor as an example, but the present invention is not limited to this. It is also possible to use a method of adjusting the output voltage VOUT by inserting a resistance element in series with the diode. A bipolar transistor or a diode element in which the collector terminal and the base terminal are connected can be used, and a diode-connected MOS transistor can also be combined to form a configuration in which these elements are mixed.

  In addition, an NMOS transistor is used instead of a PMOS transistor that receives an input voltage signal, and a constant current source is connected to the source terminal of the NMOS transistor, so that the output voltage is determined against a transient voltage decrease of the input voltage signal. It can also be set as the structure maintained at a voltage.

It is a principle diagram of the present invention. It is a circuit diagram showing an embodiment of the present invention. It is a circuit diagram which shows background art.

DESCRIPTION OF SYMBOLS 1 Voltage conversion part 2 Later stage circuit A Input terminal C1, C2, CC capacitive element D Diode part D1-Dn Diode IS Constant current source M1, Q1, Q3, Q5, Q7, Q9 PMOS transistor M2, Q2, Q4, Q6, Q8 , Q10, Q14 NMOS transistor R2 Resistance element VIN Voltage supply unit VOUT Output terminal

Claims (8)

An input transistor whose input voltage signal is input to the base terminal or the gate terminal;
A constant current source for supplying a bias current to the emitter terminal or the source terminal of the input transistor;
A capacitive element having one end connected to a path from the previous Kijo current source to the emitter terminal or source terminal of the input transistor,
A constant voltage circuit comprising: an emitter or a source follower circuit that receives a voltage signal generated at one end of the capacitor and outputs a constant voltage.   The constant voltage circuit according to claim 1, wherein the other end of the capacitive element is connected to a power supply voltage or a ground voltage.   The constant voltage circuit according to claim 1, further comprising at least one diode in a path connecting the input transistor and the constant current source and extending from the input transistor to the capacitive element. .   The constant voltage circuit according to claim 3, wherein the diode is a diode-connected transistor. With a bandgap reference circuit,
The input voltage signal, the constant voltage circuit according to at least any one of claims 1 to 4, wherein the output from the band-gap reference circuit. A constant voltage supply system for supplying a predetermined voltage to a subsequent circuit,
A voltage supply for supplying an input voltage signal;
An input transistor to which the input voltage signal is input to a base terminal or a gate terminal;
A constant current source for supplying a bias current to the emitter terminal or the source terminal of the input transistor;
A capacitive element having one end connected to a path connecting the input transistor and the constant current source;
A constant voltage supply system comprising: an emitter or a source follower circuit that receives a voltage signal generated at one end of the capacitive element and supplies a constant voltage to the subsequent circuit. Inputting an input voltage signal to the base terminal or gate terminal of the input transistor;
Flowing a bias current from a constant current source to the emitter terminal or the source terminal of the input transistor;
Level conversion of the input voltage signal according to the conduction control voltage of the input transistor by the bias current, and outputting a voltage signal from the emitter terminal or the source terminal ;
Providing a low-pass filter characteristic by a capacitive element having one end connected to a path from the constant current source to the emitter terminal or the source terminal of the input transistor and the other end connected to a power supply voltage or a ground voltage ;
And a step of outputting a voltage from an emitter follower circuit or a source follower circuit using the voltage signal as an input .   The conduction control voltage includes a gate-source voltage when a drain current flows in a MOS transistor, a base-emitter voltage when a collector current flows in a bipolar transistor, and a forward voltage of a diode. Item 8. The constant voltage supply method according to Item 7.

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