JPS6296719U - - Google Patents
Info
- Publication number
- JPS6296719U JPS6296719U JP18804485U JP18804485U JPS6296719U JP S6296719 U JPS6296719 U JP S6296719U JP 18804485 U JP18804485 U JP 18804485U JP 18804485 U JP18804485 U JP 18804485U JP S6296719 U JPS6296719 U JP S6296719U
- Authority
- JP
- Japan
- Prior art keywords
- control transistor
- emitter
- operational amplifier
- field effect
- current limiting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Description
第1図は本考案の一実施例である直流安定化電
源回路の保護回路を示す回路図である。第2図お
よび第3図は従来の保護回路の一例を示す回路図
である。
2……制御トランジスタ、3……演算増幅器、
4……抵抗、5……直流電圧源、6……FET。
FIG. 1 is a circuit diagram showing a protection circuit for a DC stabilized power supply circuit according to an embodiment of the present invention. FIGS. 2 and 3 are circuit diagrams showing an example of a conventional protection circuit. 2... Control transistor, 3... Operational amplifier,
4...Resistor, 5...DC voltage source, 6...FET.
Claims (1)
に出力端子が接続されると共に、一方の入力端子
が上記制御トランジスタのエミツタに接続され、
他方の入力端子が電流制限用の抵抗を介して直流
電圧源に接続された演算増幅器と、 ソースが上記制御トランジスタのエミツタに接
続され、ドレインが上記演算増幅器と上記電流制
限用の抵抗とし接続点に接続されると共に、ゲー
トが所定の電位に保持された電界効果トランジス
タとを備えが成る直流安定化電源回路の保護回路
。[Claims for Utility Model Registration] An output terminal is connected to the base of a control transistor that controls the output voltage, and one input terminal is connected to the emitter of the control transistor,
An operational amplifier whose other input terminal is connected to a DC voltage source via a current limiting resistor, a source connected to the emitter of the control transistor, and a drain connected to the operational amplifier and the current limiting resistor. 1. A protection circuit for a DC stabilized power supply circuit, comprising a field effect transistor connected to a field effect transistor and having a gate held at a predetermined potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18804485U JPS6296719U (en) | 1985-12-06 | 1985-12-06 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18804485U JPS6296719U (en) | 1985-12-06 | 1985-12-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6296719U true JPS6296719U (en) | 1987-06-20 |
Family
ID=31139047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18804485U Pending JPS6296719U (en) | 1985-12-06 | 1985-12-06 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6296719U (en) |
-
1985
- 1985-12-06 JP JP18804485U patent/JPS6296719U/ja active Pending
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