JPS62168659U - - Google Patents
Info
- Publication number
- JPS62168659U JPS62168659U JP5644786U JP5644786U JPS62168659U JP S62168659 U JPS62168659 U JP S62168659U JP 5644786 U JP5644786 U JP 5644786U JP 5644786 U JP5644786 U JP 5644786U JP S62168659 U JPS62168659 U JP S62168659U
- Authority
- JP
- Japan
- Prior art keywords
- package
- pin
- insertion hole
- top surface
- chip select
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000037431 insertion Effects 0.000 claims description 4
- 238000003780 insertion Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図はこの考案の実施例であるＩＣパツケー
ジの構造を表す斜視図、第２図は同ＩＣパツケー
ジを回路基板上に積層実装した状態を表す図、第
３図は第２図に示した場合の具体的な回路例を表
す図である。
１…ＩＣパツケージ、Ｐ１，Ｐ２，Ｐ３，Ｐ４
…チツプセレクトピン、Ｐ５，Ｐ６，Ｐｎ…共通
ラインのピン、Ｓ１〜Ｓ６，Ｓｎ…ピン挿入口。
Figure 1 is a perspective view showing the structure of an IC package that is an embodiment of this invention, Figure 2 is a diagram showing the IC package stacked and mounted on a circuit board, and Figure 3 is the same structure as shown in Figure 2. FIG. 3 is a diagram showing a specific circuit example in this case. 1...IC package, P1, P2, P3, P4
...Chip select pin, P5, P6, Pn... Common line pin, S1 to S6, Sn... Pin insertion slot.
Claims (1)
に実装するＩＣパツケージにおいて、 複数のチツプセレクトピンが１列に形成されて
いるＩＣパツケージの上面にそのＩＣパツケージ
の各ピンと同じ位置に他のＩＣパツケージのピン
挿入口を設け、更に共通ラインのピンにその直上
のピン挿入口を接続し、各チツプセレクトピンに
ピン配列方向に１つずれたピン挿入口を接続した
ことを特徴とするＩＣパツケージ。[Claim for Utility Model Registration] In an IC package in which multiple IC packages are stacked one above the other and mounted on a circuit board, a plurality of chip select pins are formed in a row on the top surface of the IC package, and each pin of the IC package is mounted on the top surface of the IC package. A pin insertion hole for another IC package is provided at the same position, and the pin insertion hole directly above it is connected to a pin on the common line, and a pin insertion hole shifted by one position in the pin arrangement direction is connected to each chip select pin. An IC package featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5644786U JPS62168659U (en) | 1986-04-14 | 1986-04-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5644786U JPS62168659U (en) | 1986-04-14 | 1986-04-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62168659U true JPS62168659U (en) | 1987-10-26 |
Family
ID=30885255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5644786U Pending JPS62168659U (en) | 1986-04-14 | 1986-04-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62168659U (en) |
-
1986
- 1986-04-14 JP JP5644786U patent/JPS62168659U/ja active Pending
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