JPS62166540U - - Google Patents
Info
- Publication number
- JPS62166540U JPS62166540U JP5427186U JP5427186U JPS62166540U JP S62166540 U JPS62166540 U JP S62166540U JP 5427186 U JP5427186 U JP 5427186U JP 5427186 U JP5427186 U JP 5427186U JP S62166540 U JPS62166540 U JP S62166540U
- Authority
- JP
- Japan
- Prior art keywords
- shot
- output
- pulse
- generates
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Ultra Sonic Daignosis Equipment (AREA)
Description
第1図は本考案の一実施例を示すブロツク図、
第2図は第1図に示す各部の波形を示すタイムチ
ヤートである。
1……ワンシヨツトマルチバイブレータ、2…
…インバータ、3……ANDゲート、4……ワン
シヨツトマルチバイブレータ、5……インバータ
、6……セレクタ、7……RAM、101……W
RITEパルス入力端子、102……READパ
ルス入力端子、103……WRITEアドレス入
力端子、104……READアドレス入力端子、
105……データ入力端子、106……データ出
力端子、a……WRITEパルス、b……ワンシ
ヨツト出力、c……READパルス、d……RE
ADパルス反転信号、e……ANDゲート出力、
f……ワンシヨツト出力、g……WRITEパル
ス。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a time chart showing the waveforms of each part shown in FIG. 1...One-shot multivibrator, 2...
...Inverter, 3...AND gate, 4...One shot multivibrator, 5...Inverter, 6...Selector, 7...RAM, 101...W
RITE pulse input terminal, 102...READ pulse input terminal, 103...WRITE address input terminal, 104...READ address input terminal,
105...Data input terminal, 106...Data output terminal, a...WRITE pulse, b...One shot output, c...READ pulse, d...RE
AD pulse inversion signal, e...AND gate output,
f...One shot output, g...WRITE pulse.
Claims (1)
シヨツト出力を発生するワンシヨツトマルチバイ
ブレータと、READパルスを反転してREAD
パルス反転信号を出力する第1のインバータと、
前記第1のワンシヨツト出力と前記READパル
ス反転信号との論理積をとつてANDゲート出力
を発生するANDゲートと、前記ANDゲート出
力を入力とし第2のワンシヨツト出力を発生する
第2のワンシヨツトマルチバイブレータと、前記
第2のワンシヨツト出力を反転して第2のWRI
TEパルスを出力する第2のインバータと、アド
レス信号を切り換えるセレクタと、RAMとを含
むことを特徴とするバツフア回路。 A one-shot multivibrator that receives the first WRITE pulse as input and generates the first one-shot output, and a one-shot multivibrator that inverts the READ pulse and generates a READ pulse.
a first inverter that outputs a pulse inversion signal;
an AND gate that generates an AND gate output by calculating the AND of the first one-shot output and the READ pulse inversion signal; and a second one-shot multi-function circuit that receives the AND gate output as input and generates a second one-shot output. vibrator and a second WRI by inverting the second one-shot output.
A buffer circuit comprising a second inverter that outputs a TE pulse, a selector that switches an address signal, and a RAM.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5427186U JPS62166540U (en) | 1986-04-10 | 1986-04-10 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5427186U JPS62166540U (en) | 1986-04-10 | 1986-04-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62166540U true JPS62166540U (en) | 1987-10-22 |
Family
ID=30881107
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5427186U Pending JPS62166540U (en) | 1986-04-10 | 1986-04-10 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62166540U (en) |
-
1986
- 1986-04-10 JP JP5427186U patent/JPS62166540U/ja active Pending
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