JPH0480132U - - Google Patents

Info

Publication number
JPH0480132U
JPH0480132U JP12440190U JP12440190U JPH0480132U JP H0480132 U JPH0480132 U JP H0480132U JP 12440190 U JP12440190 U JP 12440190U JP 12440190 U JP12440190 U JP 12440190U JP H0480132 U JPH0480132 U JP H0480132U
Authority
JP
Japan
Prior art keywords
arbitrary
amount
delay amount
memory
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12440190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12440190U priority Critical patent/JPH0480132U/ja
Publication of JPH0480132U publication Critical patent/JPH0480132U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Pulse Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例による可変デイジ
タル遅延回路のブロツク図、第2図は従来の可変
デイジタル遅延回路のブロツク図である。 図において、1はシフトレジスタ、2はマルチ
プレクサ、3は遅延量設定スイツチ、4はメモリ
、5は書き込みカウンタ、6は読み出しカウンタ
、7はメモリR/Wジエネレータ、8は出力パル
ス生成レジスタを示す。なお、図中、同一符号は
同一、または相当部分を示す。
FIG. 1 is a block diagram of a variable digital delay circuit according to an embodiment of this invention, and FIG. 2 is a block diagram of a conventional variable digital delay circuit. In the figure, 1 is a shift register, 2 is a multiplexer, 3 is a delay amount setting switch, 4 is a memory, 5 is a write counter, 6 is a read counter, 7 is a memory R/W generator, and 8 is an output pulse generation register. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 任意のパルス幅のデイジタルパルスをその繰り
返しの範囲内で、外部からの設定値に応じて任意
時間量遅延させる回路において、遅延量を発生さ
せるのにメモリを用い、任意かつ長時間の遅延量
を発生させることを特徴とする可変デイジタル遅
延回路。
In a circuit that delays a digital pulse of an arbitrary pulse width by an arbitrary amount of time within its repetition range according to an externally set value, a memory is used to generate the delay amount, and an arbitrary and long delay amount can be generated. A variable digital delay circuit characterized by generating
JP12440190U 1990-11-26 1990-11-26 Pending JPH0480132U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12440190U JPH0480132U (en) 1990-11-26 1990-11-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12440190U JPH0480132U (en) 1990-11-26 1990-11-26

Publications (1)

Publication Number Publication Date
JPH0480132U true JPH0480132U (en) 1992-07-13

Family

ID=31872054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12440190U Pending JPH0480132U (en) 1990-11-26 1990-11-26

Country Status (1)

Country Link
JP (1) JPH0480132U (en)

Similar Documents

Publication Publication Date Title
JPH0480132U (en)
JPS6319880B2 (en)
JPH0255346U (en)
JPS60119138U (en) Pulse generation circuit
JPH039027U (en)
JPH045292B2 (en)
JPH048538U (en)
JPH032281U (en)
JPH04102080U (en) waveform generator
JPH036578U (en)
JPS62166540U (en)
JPS6289880U (en)
JPS60102690U (en) Radiation measuring instrument noise prevention circuit
JPH02148474U (en)
JPS61131130U (en)
JPH01180669U (en)
JPH0275859U (en)
JPH0385587U (en)
JPH0161682U (en)
JPH0262833U (en)
JPS5383665A (en) Sound source generator
JPH036311U (en)
JPH032280U (en)
JPS63153625U (en)
JPS6310471U (en)