JPS6216551B2 - - Google Patents

Info

Publication number
JPS6216551B2
JPS6216551B2 JP13782578A JP13782578A JPS6216551B2 JP S6216551 B2 JPS6216551 B2 JP S6216551B2 JP 13782578 A JP13782578 A JP 13782578A JP 13782578 A JP13782578 A JP 13782578A JP S6216551 B2 JPS6216551 B2 JP S6216551B2
Authority
JP
Japan
Prior art keywords
lead wire
copper
lead
chip
welding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13782578A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5565452A (en
Inventor
Yoshimi Watanabe
Kunio Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP13782578A priority Critical patent/JPS5565452A/ja
Publication of JPS5565452A publication Critical patent/JPS5565452A/ja
Publication of JPS6216551B2 publication Critical patent/JPS6216551B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP13782578A 1978-11-10 1978-11-10 Slug lead Granted JPS5565452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13782578A JPS5565452A (en) 1978-11-10 1978-11-10 Slug lead

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13782578A JPS5565452A (en) 1978-11-10 1978-11-10 Slug lead

Publications (2)

Publication Number Publication Date
JPS5565452A JPS5565452A (en) 1980-05-16
JPS6216551B2 true JPS6216551B2 (enrdf_load_stackoverflow) 1987-04-13

Family

ID=15207721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13782578A Granted JPS5565452A (en) 1978-11-10 1978-11-10 Slug lead

Country Status (1)

Country Link
JP (1) JPS5565452A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS588959U (ja) * 1981-07-13 1983-01-20 日本電気ホームエレクトロニクス株式会社 Dhd形ダイオ−ド

Also Published As

Publication number Publication date
JPS5565452A (en) 1980-05-16

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