JPS62165422A - Digital filter - Google Patents

Abstract

PURPOSE:To expand the length of a factor word and to improve the arithmetic accuracy of a filter by executing a part of multiplication of the small absolute value of an impulse response through a filter before one sampling time from other parts. CONSTITUTION:The serial data of LSB fast are impressed to an input terminal 1 and delayed by one sampling time respectively by delay circuits 10-1n. A multiplier group 21-2n execute multiplication of a factors a1-an corresponding to the impulse responses of the filters and an input is switched by one sampling time through a switch group 31-3n. The multiplied outputs are switched and sent to a holding circuit group 51-5n for holding the MSB of data and an adder 4 through a switch group 41-4n. The outputs of the circuit group 51-5n and the output of the circuit 4 delayed by an one-sample time delay circuit 5 and passed through a switch 6 are supplied to an adder 2. The opening time of the switch 6 is set up to a range affected by a carry on the basis of operation of a factor expanding component and filter output is obtained from a terminal 3.

Description

[Detailed description of the invention] [Industrial application field] This invention relates particularly to digital filters.

The present invention relates to a digital filter that can increase the precision of the filter by increasing the multiplier, that is, the number of significant digits of the coefficient, without increasing the clock frequency of the multiplier circuit of the digital filter.

[Conventional technology]

Conventionally, a sum of products operation is performed in a digital filter.

An example of the circuit configuration of a non-recursive (FIR) n-order digital filter is shown in FIG. 4 and will be described.

In the figure, 1 is a data input terminal, 11, 12...
・1n is a delay circuit of 1 sample time each, 21.2
2-+1·φ@2n multiplier group that multiplies the pulse response 凰i by the corresponding coefficient; 2 is an adder;

3 is an output terminal.

Next, the calculation timing in the digital filter shown in FIG. 4 will be explained with reference to FIG. 5.

In this Figure 5, 21θ, 22θ...2nθ
are the outputs of the multipliers 21 to 2n in FIG. 4, and show the states at time T and time T+1.

First, all data input and output of multipliers 11 to 1n are LSB.
(Leaat 51gn1ficant Bit)
It shall be done first and serially.

Now, assuming that the data word length is M bits and the coefficient word length is N bits, the multiplication result will be M+N bits.

That is, the number of locks required to output one word of data is M1N clocks. Furthermore, MSB (Moat 51gn1fican
tntt), the required number of clocks increases by that amount.

Next, if we assume that the impulse response of the digital filter in Fig. 4 is as shown in Fig. 3, then in Fig. 5,
The contents of the shaded areas are constant regardless of the data. That is, if the data format is two's complement, the MSB of each data is filled in the shaded area.

This also means that the number of significant digits of the multiplication coefficient in the portion where the absolute value of the impulse response is small is reduced, and is one of the causes of reducing the calculation accuracy of the filter.

To improve this point, the number of clocks within one sample time (
clock rate) must be increased.

Problems may arise in the operating speed of the circuit or in matching the clock frequency of the system including the filter.

[Problem that the invention seeks to solve]

With conventional digital filters such as those mentioned above, it is necessary to increase the calculation clock rate, which also causes problems such as the circuit operating speed or the matching with the clock frequency of the system that includes the filter. The problem was that the accuracy was not good.

This invention was made to solve this problem, and increases the number of significant digits in some coefficients without increasing the calculation clock rate.

The purpose of this invention is to obtain a digital filter that can improve the accuracy of calculations.

[Means for solving problems]

The digital filter according to the present invention is a digital filter equipped with a multiplier circuit having an LSB first serial data input terminal, and the input terminal of the multiplier group constituting the multiplier circuit is 1? a first switch group for switching the sample time, a second switch group for switching the output of the multiplier group, a data holding circuit group connected to each switch of the second switch group, and this data holding circuit group. a first addition circuit that adds the outputs of the above, a second addition circuit connected to the second switch group, a one-sample time delay circuit connected to the second addition circuit, and this delay circuit. and a switch for connecting the output of the filter to the first addition circuit, so that part of the multiplication of the part of the impulse response of the filter having a small absolute value can be performed one sample time before the other parts. be.

[Effect]

In this invention, part of the multiplication of the portion of the impulse response of the filter having a small absolute value is performed one sample time before the other portions. Then, the coefficient word length is expanded to the shaded area in FIG. 5, that is, the area filled with the MSB of each data.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of a digital filter according to the present invention, and shows a case where the present invention is applied to a non-recurrence type (FIR) digital filter.

In the figure, 1 is an input terminal to which LSB first serial data is applied, io, 1i...1n are delay circuits each having one sample time, 21, 22, so...2
n is a coefficient a corresponding to the impulse response of the filter
Multiplier group for multiplying I-8n, 31゜32...3
n is a first switch group that switches the inputs of the multiplier groups 21 to 2n at one sample time, and 41°42...4n is a data holding circuit that holds the MSB of the data of the outputs of the multiplier groups 21 to 2n. This is a second switch group for switching between the groups 51, 52, . . . 5n and the second adder circuit 4.

The data holding circuit groups 51 to 5n are connected to each switch of the second switch group 41 to 4n.

A first circuit that adds the outputs of the two-digit data holding circuit groups 51 to 5n.
5 is a delay circuit that is connected to the second adder circuit 4 connected to the second switch group 21 to 2n and delays the output of the adder circuit 4 by one sample time; 6 is a delay circuit that delays the output of the delay circuit 5 by one sample time; A switch 3 connected to the first adder circuit 2 is an output terminal.

Here, the coefficient word length is not expanded in the multiplier 26 which multiplies the impulse response of the filter by a further coefficient a6, and a multiplier input/output switch and a data holding circuit are not provided.

Therefore, the - part of the multiplication of the part with the small absolute value of the impulse response of the filter is performed on the other part 1f before the sample time.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.

This FIG. 2 is a time chart used to explain the operation of FIG.
2n output, and is shown for time 1 T and time T+1. The shaded area in the figure is the area where the coefficient word length is expanded.

FIG. 3 shows the filter twin pulse response in FIGS. 1 and 4.

First, the calculation of this coefficient word length expansion part is performed one sample time before. Then, depending on the multiplied coefficient, the MSB of data is held in the data holding circuit groups 51 to 5n at respective timings at times when the MSB of data is successively outputted thereafter.

Then, at the next clock timing, the multiplier groups 21 to 2n
The input of 1″!7! is input by the first switch group 31 to 3n.
7 samples, and the output is switched to the second adder circuit 4 side by the second switch group 41 to 4n.

That is, the necessary MSB is stored in the data holding circuit groups 51 to 5n.
During this time, the coefficient word length extension portion of the data after one sample time is calculated.

Next, the result of the calculation is delayed by one sample time in the delay circuit 5, and is input to the first addition circuit 2 at a predetermined timing. Then, switch 6 is activated at time T6 in FIG.
It shall be open for a period of . Here, the length of this time T6 is set to be the range in which the carry reaches the maximum due to the calculation of the coefficient extension. When the data format is two's complement, the second switch group 41 to 4n and the switch 6 output "0" to unconnected terminals.

In this way, the number of significant digits of the coefficients is expanded and the accuracy of the filter is improved.

〔Effect of the invention〕

As explained above, according to the present invention, part of the multiplication of the part with the small absolute value of the impulse response of the filter is performed with respect to other parts before ■ the sample time, so the calculation clock Since the coefficient word length can be expanded without increasing the rate e and the calculation accuracy of the filter can be increased, the practical effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a digital filter according to the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is an impulse response of the filter of FIGS. 1 and 4. FIG. 4 is a configuration diagram showing an example of a conventional digital filter, and FIG. 5 is a time chart for explaining the operation of FIG. 4. 1...Input terminal, 2...First addition circuit, 4...
...Second addition circuit, 5...Delay circuit, 6...
・Switch, 21-2n... Multiplier group, 31-3n
...First switch group, 41 to 4n ...Second
switch group, 51 to 5n...data holding circuit group.

Claims (1)

[Claims] A digital filter comprising a multiplier circuit having an LSB first serial data input terminal, the digital filter comprising: a first switch group for switching the input of the multiplier group constituting the multiplier circuit at one sample time; a second switch group for switching, a data holding circuit group connected to each switch of the second switch group, a first addition circuit for adding the outputs of the data holding circuit group, and the second switch group.
a second adder circuit connected to the switch group;
a 1-sample time delay circuit connected to the adder circuit;
a switch that connects the output of the delay circuit to the first addition circuit, and a switch that connects the output of the delay circuit to the first addition circuit, and multiplies a portion of the filter impulse response with a small absolute value by 1 for the other portion.
A digital filter characterized in that it can be operated before a sample time.