JPS6138494B2 - - Google Patents
Info
- Publication number
- JPS6138494B2 JPS6138494B2 JP56134058A JP13405881A JPS6138494B2 JP S6138494 B2 JPS6138494 B2 JP S6138494B2 JP 56134058 A JP56134058 A JP 56134058A JP 13405881 A JP13405881 A JP 13405881A JP S6138494 B2 JPS6138494 B2 JP S6138494B2
- Authority
- JP
- Japan
- Prior art keywords
- register
- bit
- adder
- digital differential
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004364 calculation method Methods 0.000 description 21
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/64—Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing increments; Other incremental computing devices for solving difference equations
Description
【発明の詳細な説明】 本発明はデイジタル微分解析器に関する。[Detailed description of the invention] The present invention relates to a digital differential analyzer.
既知のデイジタル微分解析器における基本演算
は積分である。積分はｘ、ｙの２つの入力が与え
られたとき
Ｚ＝∫ydx
を満足する。これは微分形を用いて
dz＝ydx
となる。デイジタル微分解析器における積分器で
はdx，dzとして量子化を行つた有限の微小量△
ｚ，△ｚについて
△ｚ＝ｙ△ｘ
の演算を行う。デイジタル微分解析器における積
分器の基本構成を第１図に示す。Ｙレジスタ１に
は、初期値y0がセツトされ、Ｙレジスタ増分パル
スIPが入力線５に入力するたびに、加算器４ａを
介して、加算され、Ｙレジスタ１の内容は、変化
分△ｙにより
yi＝yi−１＋△ｙ
となる。Ｙレジスタ１の出力は、ANDゲート３
を介して加算器４ｂの入力線８に接続される。Ｓ
レジスタ２の出力は加算器４ｂの入力線９に接続
される。ANDゲート３の入力線７に演算パルス
APが入力されるとＹレジスタ１の内容とＳレジ
スタ２の内容が加算器４ｂを介して加算され、加
算結果は接続線１０を経由してＳレジスタ２に格
能される。OVPはオーバフローパルスである。
Ｙレジスタ１の場合は、ANDゲート３への演算
パルスAPと演算パルスAPの入力する間になされ
る。 The basic operation in known digital differential analyzers is integration. Integration satisfies Z=∫ydx when two inputs, x and y, are given. This becomes dz=ydx using the differential form. The integrator in the digital differential analyzer uses finite minute quantities △ which are quantized as dx and dz.
For z and △z, perform the calculation △z=y△x. FIG. 1 shows the basic configuration of an integrator in a digital differential analyzer. An initial value y 0 is set in the Y register 1, and each time the Y register increment pulse IP is input to the input line 5, it is added via the adder 4a, and the contents of the Y register 1 are equal to the change Δy. Therefore, yi=yi− 1 +△y. The output of Y register 1 is AND gate 3
The input line 8 of the adder 4b is connected to the input line 8 of the adder 4b. S
The output of register 2 is connected to input line 9 of adder 4b. Operation pulse on input line 7 of AND gate 3
When AP is input, the contents of Y register 1 and S register 2 are added via adder 4b, and the addition result is output to S register 2 via connection line 10. OVP is an overflow pulse.
In the case of the Y register 1, this is done between the input of the calculation pulse AP and the calculation pulse AP to the AND gate 3.
第２図にｎビツト直列演算方式のデイジタル微
分解析器の構成図を示す。Ｙレジスタ１、Ｓレジ
スタ２は各々ｎビツトであり、Ｙレジスタ１は接
続線１３を介して加算器４ｂに接続され、Ｓレジ
スタ２は接続線１４を介して加算器４ｂに接続さ
れ、加算結果は接続線１５を経由しとＳレジスタ
２に格納される。加算器４ｂの出力はキヤリーフ
リツプフロツプ１２に接続され、各ビツトごとの
加算演算にともなうキヤリー信号を保持し、次ビ
ツトの加算演算の入力として接線１６を介して、
加算器４ｂの入力となる。キヤリーフロツプフロ
ツプ１２の出力は、ANDゲート３により、加算
タイミングtnのときのキヤリーをオーバフローパ
ルスOVPとして取り出す。なお、この図におい
てＹレジスタ１の増分回路部分は省略して示して
ある。 FIG. 2 shows a configuration diagram of an n-bit serial calculation type digital differential analyzer. Y register 1 and S register 2 each have n bits, Y register 1 is connected to adder 4b via connection line 13, S register 2 is connected to adder 4b via connection line 14, and the addition result is is stored in the S register 2 via the connection line 15. The output of the adder 4b is connected to a carry flip-flop 12, which holds the carry signal associated with the addition operation for each bit, and is used as an input for the addition operation of the next bit via the tangent line 16.
It becomes an input to adder 4b. The output of the carry flop flop 12 is taken out by the AND gate 3 as the carry at the addition timing tn as an overflow pulse OVP. In this figure, the increment circuit portion of the Y register 1 is omitted.
第３図に実用に共する直列演算方式のデイジタ
ル微分解析器の構成図を示す。YMレジスタ１９
は（ｎ×ｍ）ビツトで構成され、ｎビツトのレジ
スタがｍ個直列に接続された構成となる。SMレ
ジスタ２０は（ｎ×ｍ）ビツトで構成され、ｎビ
ツトのレジスタがｍ個直列に接続された構成とな
る。YMレジスタ１９の内容とSMレジスタ２０
の内容は加算器４ｂを介して加算され、加算結果
はSMレジスタ２０に格納され、オーバフローは
オーバフローレジスタ２１に格納される。加算は
S1＋Y1、S2＋Y2、………と順次実行され（Si＋
Yi）の加算演算には（Si−１＋Yi−１）以前に実
行されたオーバフローが反映される。本構成の直
列演算方式による演算時間は、１ビツトの加算に
要する時間を△ｔ時間とするとｎビツトの演算時
間は
ｎ×△ｔ
となり、ｍ個の積分演算に要する時間は
ｍ×ｎ×△ｔ
となる。直列演算方式によるデイジタル微分解析
器はハードウエア規模が小さいという利点はある
が、演算速度がおそいという欠点をもつ。演算を
高速化する手段として第２図の構成から成る積分
器をデイジタル微分解析器の１演算単位として、
ｍ個の積分単位を構成し並列に演算を実行せしめ
る方法がある。本方式は一般に並列演算方式と呼
ばれており、演算時間は、
ｎ×△ｔ
と高速になる。しかし、並列演算方式はデイジタ
ル微分解析器の構成要素として、ｎ個の加算器と
ｎビツトのレジスタが2m個必要となる。 FIG. 3 shows a block diagram of a digital differential analyzer using a serial calculation method that is suitable for practical use. YM register 19
is composed of (n×m) bits, and has a configuration in which m n-bit registers are connected in series. The SM register 20 is composed of (n×m) bits, and has a configuration in which m registers of n bits are connected in series. Contents of YM register 19 and SM register 20
The contents of are added via the adder 4b, the addition result is stored in the SM register 20, and the overflow is stored in the overflow register 21. The addition is
S 1 +Y 1 , S 2 +Y 2 , etc. are executed sequentially (Si +
The addition operation of Yi) reflects the overflow executed before (Si- 1 +Yi- 1 ). The calculation time using the serial calculation method of this configuration is: If the time required to add one bit is △t time, the calculation time for n bits is n×△t, and the time required for m integral calculations is m×n×△. It becomes t. Digital differential analyzers using a serial calculation method have the advantage of small hardware scale, but have the disadvantage of slow calculation speed. As a means of speeding up calculations, an integrator with the configuration shown in Figure 2 is used as one calculation unit of a digital differential analyzer.
There is a method of constructing m integral units and performing calculations in parallel. This method is generally called a parallel calculation method, and the calculation time is as fast as n×Δt. However, the parallel operation method requires n adders and 2m n-bit registers as components of the digital differential analyzer.
本発明の目的は、直列演算方式と並列演算方式
の欠点を補い、利点をとりいれた構成のデイジタ
ル微分解析器を供するにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a digital differential analyzer having a structure that compensates for the drawbacks of the serial calculation method and the parallel calculation method and takes advantage of the advantages.
以下、第４図に示す本発明の一実施例について
説明する。本デイジタル微分解析器の基本構成要
素はｍビツトのレジスタｎ個から成るＹレジスタ
群とｍビツトのレジスタｎ個から成るＳレジスタ
群とｎビツト加算器とオーバフローレジスタから
成る。なお、増分回路部分は省略して示してあ
る。すなわち、本発明によれば図に示す如く、ｍ
ビツトのレジスタｎ個を並列に配置し、各レジス
タの１ビツト目を集合したレジスタをY1レジス
タ、２ビツト目を集合したレジスタをY2レジス
タ、以下同様にしてｍビツト目を集合したレジス
タをYmレジスタとなし、ｍ個のＹレジスタ群を
構成する。 An embodiment of the present invention shown in FIG. 4 will be described below. The basic components of this digital differential analyzer are a Y register group consisting of n m-bit registers, an S register group consisting of n m-bit registers, an n-bit adder, and an overflow register. Note that the incremental circuit portion is omitted from illustration. That is, according to the present invention, as shown in the figure, m
N bit registers are arranged in parallel, and the register that collects the first bit of each register is the Y1 register, the register that collects the second bit is the Y2 register, and so on. The Ym register constitutes a group of m Y registers.
同様に、ｍビツトのレジスタｎ個を並列に配置
し、各レジスタの１ビツト目を集合したレジスタ
をS1レジスタ、２ビツト目を集合したレジスタを
S2レジスタ、以下同様にしてｍビツト目を集合し
たレジスタをSmレジスタとなし、ｍ個のＳレジ
スタ群を構成する。YM1レジスタ２２とSM1レ
ジスタ２５は接続線２９と接続線３２を介して、
加算器２８に接続する。YM1レジスタ２２の内
容とSM1レジスタ２５の内容は加算器２８によつ
て加算演算が実行され、その加算結果はSM1レジ
スタ２５に接続線３５を経由して格納される。以
下同様にして、YM2＋SM2、……、YMn＋SMn
の演算が並行して実行される。１ビツトの加算に
要する時間を△t′とすると本構成になるｎビツト
ｍ個の積分演算に要する時間は
ｍ×△t′
となり、直列演算に比し、演算時間は１／ｎに短
縮される。 Similarly, n registers of m bits are arranged in parallel, and the register that collects the 1st bit of each register is the S1 register, and the register that collects the 2nd bit of each register is the S1 register.
The S2 register, and the like, the register in which the m-th bit is collected is defined as the Sm register, forming a group of m S registers. YM1 register 22 and SM1 register 25 are connected via connection line 29 and connection line 32,
Connect to adder 28. An adder 28 performs an addition operation on the contents of the YM1 register 22 and the contents of the SM1 register 25, and the result of the addition is stored in the SM1 register 25 via a connection line 35. Similarly, YM2+SM2, ..., YMn+SMn
operations are executed in parallel. If the time required for addition of 1 bit is △t', the time required for integral operation of m pieces of n bits in this configuration is m×△t', and compared to serial operation, the operation time is reduced to 1/n. Ru.
以上説明した如く、本発明によれば、直列演算
方式と並列演算方式の各々の欠点をなくし、それ
らの利点を有する高速、安価なデイジタル微分解
析器を得ることができる。 As described above, according to the present invention, it is possible to eliminate the drawbacks of the serial calculation method and the parallel calculation method, and to obtain a high-speed, inexpensive digital differential analyzer that has the advantages thereof.
第１図は、デイジタル微分解析器を説明するた
めのブロツク結線図、第２図は従来のｎビツト直
列演算方式のデイジタル微分解析器を示すブロツ
ク結線図、第３図は従来のｍ個の積分要素をもつ
直列演算方式のデイジタル微分解析器を示すブロ
ツク結線図、第４図は本発明の直並列デイジタル
微分解析器の一実施例を示すブロツク結線図であ
る。
２２，２３，２４：Ｙレジスタ群、２５，２
６，２７：Ｓレジスタ群、２８：ｎビツトの加算
器。
Figure 1 is a block wiring diagram for explaining a digital differential analyzer, Figure 2 is a block wiring diagram showing a conventional n-bit serial calculation type digital differential analyzer, and Figure 3 is a conventional digital differential analyzer for m integrals. FIG. 4 is a block diagram showing an embodiment of the serial-parallel digital differential analyzer of the present invention. 22, 23, 24: Y register group, 25, 2
6, 27: S register group, 28: n-bit adder.
Claims (1)
集合して構成したｍビツトのレジスタをｎ個並列
に配置して成るＹレジスタ群と、対応する各ビツ
トを各々集合して構成したｍビツトのレジスタを
ｎ個並列に配置して成るＳレジスタ群とを具備
し、加算演算をなすことを特徴とするデイジタル
微分解析器。1 A Y register group consisting of n m-bit registers arranged in parallel, each consisting of an n-bit adder and each corresponding bit set, and an m-bit register group consisting of n m-bit registers arranged in parallel, each consisting of a set of corresponding bits. A digital differential analyzer characterized in that it is equipped with an S register group consisting of n registers arranged in parallel, and performs addition operations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56134058A JPS5837742A (en) | 1981-08-28 | 1981-08-28 | Digital differential analyzer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56134058A JPS5837742A (en) | 1981-08-28 | 1981-08-28 | Digital differential analyzer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5837742A JPS5837742A (en) | 1983-03-05 |
| JPS6138494B2 true JPS6138494B2 (en) | 1986-08-29 |
Family
ID=15119376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56134058A Granted JPS5837742A (en) | 1981-08-28 | 1981-08-28 | Digital differential analyzer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5837742A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327030Y2 (en) * | 1986-10-27 | 1991-06-11 |
-
1981
- 1981-08-28 JP JP56134058A patent/JPS5837742A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5837742A (en) | 1983-03-05 |
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