JPS6216469B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a control method for a magnetic bubble memory used as a storage device for electronic computing devices and the like.

(2) Background of the technology Magnetic bubble utilization devices that use magnetic bubbles to store information, perform logical operations, etc. are nonvolatile, have high storage density, and low power consumption, and are solid-state devices that do not contain any mechanical elements. Because it is an element, it has various characteristics such as extremely high reliability, and is therefore expected to have a promising future as a large-capacity memory.

In this magnetic bubble memory element, a thin film of magnetic garnet is formed by liquid phase epitaxial growth on a single crystal substrate of gadolinium, gallium, and garnet, and patterns such as Taber or half-disk are formed in matrix on top of the thin film of permalloy. A bubble propagation path is formed, and the bubbles generated by a bubble generator are guided to the propagation path, and information is stored as "1" if there are bubbles in the pattern, and "0" if there are no bubbles. It's getting old. The writing and reading of information into the element is controlled by a magnetic bubble memory control circuit.

(3) Prior Art and Problems FIG. 1 is a diagram for explaining a conventional magnetic bubble memory control circuit. In the figure, 1 is a control circuit, 2 is a power-on reset circuit, 3 is a clock generator, 4 is a sequencer, 5 is a controller, and 6 is a timing generator.

In the conventional control circuit shown in FIG. 1, power-on reset is canceled regardless of the clock. This has resulted in the drawback that the control circuit may malfunction due to the power-on reset being canceled even though the clock is not output, or the clock being output when the clock waveform is not normal.

(4) Object of the Invention In view of the above-mentioned drawbacks of the conventional art, it is an object of the present invention to provide a control system that prevents malfunctions of a magnetic bubble memory control circuit when power-on reset is released.

(5) Structure of the Invention According to the present invention, the object is to provide a magnetic bubble memory control circuit including a sequencer, a controller, a clock generator, a timing generator, and a power-on reset circuit for controlling a magnetic bubble memory. A counter is connected to the clock generator, and after counting a certain number of clocks when the power is turned on, the counter sends a power-on reset signal to control the circuits of the sequencer, controller, timing generator, etc. This is achieved by providing a magnetic bubble memory control method characterized in that malfunctions at power-on are prevented by canceling the reset of the magnetic bubble memory.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram for explaining the magnetic bubble memory control method according to the present invention. In the figure, 7 is a control circuit including the following circuits, 8 is a power-on reset circuit that monitors the power supply and opens the gate when the specified voltage is reached, 9 is a clock generator, and 1
0 is a sequencer, 11 is a controller, 12 is a timing generator, and 13 is a clock that outputs when the power supply voltage exceeds a specified voltage.
NAND circuits 14 each indicate a counter for counting the number of clocks required to release the power-on reset.

FIG. 3 is a diagram showing a timing chart in the circuit of FIG. 2. In the figure, the input power supply voltage, the voltage output from the power-on reset circuit, the clock waveform output from the clock generator, the clock counted by the counter, and the power-on reset signal output from the counter to the sequencer, etc. are shown respectively.

Next, the magnetic bubble memory control method of the present invention will be explained using FIGS. 2 and 3.

When the input power is turned on and the voltage gradually rises and reaches the specified voltage V _REF , the gate of the power-on reset circuit 8 is opened and a voltage is output. Further, at the same time as the power is turned on, the clock generator 9 operates and outputs a clock pulse. This clock pulse is filtered out by the NAND gate 13 to remove the initial disturbed pulse. A counter 14 counts these clock pulses, and after counting the number N of clocks necessary for power-on reset to return the sequencer 10 etc. to the initial state, it sends out a power-on reset release signal. As a result, each circuit such as the sequencer 10 is released from reset and can resume normal operation.

(7) Effects of the Invention As explained in detail above, the magnetic bubble memory control method of the present invention detects that the power supply has reached a normal potential, and outputs a clock accordingly.
Since the power-on reset is canceled by the clock, the power-on reset will not be canceled when the clock is not output or the clock waveform is not normal, unlike in the past, and therefore the control circuit will not be canceled. This makes it possible to prevent malfunctions and is highly effective in contributing to improving the reliability of the magnetic bubble memory control circuit.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining the conventional magnetic bubble memory control method, Fig. 2 is a diagram for explaining the magnetic bubble memory control method according to the present invention, and Fig. 3 is a time chart in Fig. 2. It is a diagram. In the drawing, 7 is a control circuit, 8 is a power-on reset circuit, 9 is a clock generator, and 10 is a power-on reset circuit.
11 is a sequencer, 11 is a controller, 12 is a timing generator, 13 is a NAND circuit, and 14 is a counter.

Claims (1)

[Scope of Claims] 1. A magnetic bubble memory control circuit including a sequencer, a controller, a clock generator, a timing generator, and a power-on reset circuit for controlling a magnetic bubble memory, wherein the clock generator is provided with a counter. After the counter counts a certain number of clocks at power-on, the counter sends a power-on reset signal to release the reset of the sequencer, controller, timing generator, and other circuits. A magnetic bubble memory control method that prevents malfunction of the control circuit when it is turned on.