JPS6160503B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to magnetic bubble memory chips, and more particularly to improvements in gate circuits thereof.

Generally, magnetic thin films have magnetic domains with easy axes of magnetization in the in-plane direction, but in some types of magnetic thin films, such as orthoferrite and magnetic garnet, magnetic domains have vertical easy axes of magnetization. When a perpendicular magnetic field is applied to this thin film, the strip-shaped magnetic domains become cylindrical magnetic domains (bubble domains) at a certain magnetic field strength. This bubble domain has a diameter of several μm or less and can move freely within the magnetic thin film due to the gradient of the magnetic field. Therefore, a magnetic bubble memory device utilizes this bubble domain as a memory element. Currently, the block replica system as shown in FIG. 1 is becoming mainstream in the structure of memory chips in magnetic bubble memory devices. To briefly explain this, a plurality of information storage loops 3 are connected to a write propagation path 2 connected to a bubble generator 1, and a plurality of information storage loops 3 are connected to a read propagation path 2 connected to a detector 4. Further, a transfer-in gate 6 is provided between the write propagation path 2 and the information storage loop 3, and a transfer-out gate 7 is provided between the information storage loop 3 and the read propagation path 5. is provided. However, as the memory capacity of such memory chips increases and the number of storage loops increases, the gate becomes longer and its resistance value increases, requiring a higher power supply voltage and larger capacity. Become. The present invention has been devised to improve this drawback.

Therefore, in the present invention, in a magnetic bubble memory chip having a plurality of information storage loops connected to one information writing propagation path and one information reading propagation path, the plurality of information storage loops are connected to one information writing propagation path and one information reading propagation path. It is characterized in that it is divided into blocks, and the conductor patterns of the input gate and output gate are separated for each block.

Furthermore, in a magnetic bubble memory chip that has a plurality of information storage loops connected to one information writing propagation path and one information reading propagation path, the information storage loop is divided into a plurality of blocks. It is characterized in that the number of loop configuration bits is the same within a block and is different between blocks.

Hereinafter, embodiments of the present invention will be described in detail based on the accompanying drawings.

FIG. 2 shows the configuration of the embodiment. In the figure, numeral 1 is a bubble generator, 2 is a propagation path for information writing,
3 is an information storage loop, 4 is a detector, and 5 is a propagation path for information reading. A plurality of information storage loops 3 are provided, each of which is an information writing propagation path with one end connected to the bubble generator 1. 2 and the opposite side is connected to the detector 4.
Furthermore, these information storage loops 3 are divided into a plurality of blocks A, B, and C, and the input gates 6 _-1 , 6 _-2 , and 6 _-3 of each block are connected to the information write propagation path 2 . Output gates 7 _-1 , 7 _-2 , and 7 _-3 are provided between the information readout propagation path 5 and the information storage loop 3 . Therefore, the conductor patterns of the input gates 6 _-1 to 6 _-3 and the output gates 7 _-1 to 7 _-3 are separated for each block. Note that 8 is an eraser.

There are two ways to use this embodiment configured in this way. The first is all input gates 6 _-1
6-3 or all output gates _7-1 to _7-3 are activated simultaneously. In this case, the information writing and reading operations are the same as before, but the input gate and output gate are divided into a plurality of parts, and the resistance value of each gate is reduced, so that the power supply voltage can be lowered. However, the number of gate drive circuits required is equal to the number of blocks (number of gates).

The second usage method is to insert a blank bit between the information to be put in each block and write or read from each block sequentially.For example, as shown in Figure 3, there is a gap between the necessary information indicated by the ○ mark, as shown by the cross mark. After arranging the bits, first open the input gate _6-3 in Fig. 2 and put this C' portion into the C block, then shift the timing of one bit and open the input gate _6-2.
Put part B' into block B, then put part A' into block A. In this way, the input gates 6 _-1 to 6 _-3 can be operated with slightly different timings, so that one gate drive circuit can be used in common. Note that on the reading side, if the output gates are opened in the order of C block, B block, and A block at the same timing as on the writing side, the same information as written information can be read out.

Next, a second embodiment is shown in FIG. The configuration of this embodiment differs from the previous embodiment in that the input gate 6 is not divided into blocks (although it may be divided), and the loop configuration bits in each block A, B, and C are the same. However, it is different between blocks. For example, if the A block has n bits, the B block has n+m bits, and the C block has n+2m bits.

This embodiment thus configured is used in the following manner. First, the bit structure of the information is divided into sections corresponding to the information storage loops of each block as shown in FIG. 5, and empty bits m indicated by cross marks are inserted between the sections.
The divided information A', B', and C' are simultaneously written into each block A, B, and C via the input gate 6, respectively. When reading next time, first activate output gate _7-1 to read the information written in A block.
A' is read, then delayed by m bits, output gate _7-2 is activated, information B' written in B block is read out, information B' is further delayed by m bits, output gate _7-3 is activated, and information written in C block is read. Information C' is read out. The information read in this way has no empty bits.
Further, as in the previous embodiment, the output gate operates with timing shifted for each block, so only one gate control circuit (power supply and switching circuit) is required. Note that the output gate requires a large amount of power to split the bubble, so it was divided into each block.The input gate only has a switching function and requires a small amount of power, so it was made into one gate, but in order to lower the power supply voltage, each block was divided into two. It is better to divide it into blocks.

As explained above, the magnetic bubble memory chip of the present invention divides the information storage loop into a plurality of blocks, and by providing input/output gates in each block, it is possible to lower the power supply voltage, and the operation timing of each input/output gate can be sequentially adjusted. By shifting the gate control circuit, it is possible to use a single gate control circuit with a small capacity to perform substantially the same function as before.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a block replication method in a conventional magnetic bubble memory chip, FIG. 2 is a block diagram of a first embodiment of a magnetic bubble memory chip according to the present invention, and FIG. FIG. 4 is a diagram showing the configuration of the magnetic bubble memory chip of the second embodiment, and FIG. 5 is a diagram showing the bit configuration of the information used in the second embodiment. DESCRIPTION OF SYMBOLS 1... Bubble generator, 2... Information writing propagation path, 3... Information storage loop, 4... Detector, 5... Information reading propagation path, 6, 6 _-1 , 6 _-2 , 6 _-3 ,... Input gate , 7, 7 _-1 , 7 _-2 , 7 _-3 ...output gate,
8... Eraser.

Claims (1)

[Claims] 1. A magnetic bubble memory chip having a plurality of information storage loops connected to one information writing propagation path and one information reading propagation path,
A magnetic bubble memory chip characterized in that the information storage loop is divided into a plurality of blocks, and the conductor patterns of input gates and output gates are separated for each block. 2. In a magnetic bubble memory chip having a plurality of information storage loops connected to one information writing propagation path and one information reading propagation path,
A magnetic bubble memory chip characterized in that the information storage loop is divided into a plurality of blocks, and the number of bits constituting the loop is the same within each block and different between blocks.