JPS6013117Y2 - magnetic storage device - Google Patents

Description

[Detailed Description of the Invention] The present invention is directed to a magnetic storage device using a cylindrical magnetic domain (Bubble domain) formed in a magnetic thin plate such as orthoferrite, and in particular to a cylindrical magnetic domain storage circuit (hereinafter simply referred to as a storage loop). .

) relates to a magnetic storage device with a spare storage loop.

As shown in Fig. 1, a magnetic storage device using cylindrical magnetic domains applies a constant bias magnetic field perpendicular to the surface of a magnetic thin plate 1, such as orthoferrite, which has an axis of easy magnetization perpendicular to its surface. By adding , most of the magnetic thin plate 1 is magnetized in that direction, but a part remains magnetized in the opposite direction to form a cylindrical magnetic domain 2.

Although this magnetic domain 2 is extremely stable in terms of energy when a bias magnetic field is applied, it freely moves parallel to the surface of the magnetic thin plate 1 in the direction of a magnetic field gradient of a certain level or more.

When a T, I par pattern 3 is formed on the upper surface of the magnetic thin plate 1 using a high permeability material such as permalloy, and a rotating magnetic field HR rotating parallel to the surface of the magnetic thin plate 1 is applied, T,
The I-par pattern 3 is magnetized as indicated by the symbols 10 and -, and the magnetic domain 2 is attracted or repelled, and the magnetic domain 2 is exposed to the rotating magnetic field HR.
T, I par pattern 3 in the direction according to the rotation direction of
move along.

This movement of the magnetic domains 2 is used to perform logic operations and storage operations.

FIG. 2 is an explanatory diagram of a conventional magnetic storage device using cylindrical magnetic domains, in which the magnetic thin plate 1 has T as described above.

(2) A plurality of storage loops 4 formed by a par pattern are provided.

A propagation bus 6 is also provided in the same manner as the storage loop 4, and the storage loop 4 and the propagation bus 6 are coupled by a gate circuit 5, and the transfer of magnetic domains is carried out under the control of the gate circuit 5.

7 is a detector such as a permalloy thin film or a Hall element for detecting the presence of a magnetic domain, and 8 is a magnetic domain write/erase device.

Also, WE is a write/erase circuit, SS is a sense circuit, CC is a control circuit, CD is a gate drive circuit, and RHD is a rotating magnetic field drive circuit.

A constant rotating magnetic field is always applied to the magnetic thin plate 1 by the output of the rotating magnetic field drive circuit RHD, and the magnetic domains, that is, information within the storage loop 4 circulate within the closed loop.

For example, when one information block is composed of N bits,
Information is stored in N storage loops 4 in parallel, and the address of each information block sequentially moves in accordance with the rotating magnetic field. Correspondingly fixed.

When an information block address is specified, when the information block address arrives immediately before each gate circuit 5, a signal is sent from the control circuit CC to the gate drive circuit CD, thereby opening the gate circuit 5 and transmitting the information. is guided to the propagation bus 6.

The information, that is, the magnetic domains, induced in the propagation bus 6 moves in series in the direction of the arrow due to the rotating magnetic field, and is read out using the magnetic field change caused by the approach of the magnetic domains in the readout device 7, and the output information is output from the sense circuit Hs. and sent to processing equipment, etc.

Further, writing is performed by a write/erase circuit WE, which operates according to input information, after the magnetic domain is once erased in a write/erase device 8, for example, using a known magnetic domain eraser circuit. It forms a magnetic domain and moves along the propagation bus 6, and when it reaches each bit position, it opens the gate circuit 5 and introduces it into each storage loop 4. When this is completed, the gate circuit 5 is closed, and from then on The written information circulates within the storage loop 4.

Since the magnetic storage device as described above provides a common propagation bus 6 for a plurality of storage loops 4, only one detector 7 and one write/erase device 8 are required.

However, since the magnetic thin plate 1 currently requires a thickness of several microns to several tens of microns, it is quite difficult to manufacture a complete and large magnetic thin plate.

- Since the force detector, write/erase device, and peripheral circuits can be used in common for one magnetic thin plate, the larger the magnetic thin plate is manufactured, the cheaper the unit price per storage unit can be.

Therefore, an object of the present invention is to fabricate a large magnetic thin plate, and even if there is a defective part caused by this, a spare part for the defective part can be replaced by pre-forming, thereby substantially improving the yield of the magnetic thin plate. The object of the present invention is to provide an inexpensive magnetic storage device.

Examples will be described in detail below.

FIG. 3 is an explanatory diagram of an embodiment of the present invention, in which the same reference numerals as in FIG. 2 indicate the same parts, and circles different from those in FIG. It is.

As mentioned above, if the information block is N-bit bark, positive, 1
~No and N storage loops 4 are formed on the magnetic thin plate 1, and at arbitrary locations, preliminary loops 4a are formed adjacent to the No and N storage loops 4.

If all the storage loops 4 are complete, they operate in the same manner as in the conventional example, and the reserve loop 4a is left idle.

However, if a defective part occurs in a part of the large magnetic thin plate 1, the number of the defective accumulation loop is stored in the defective loop memory circuit LNM and the spare loop 4a is stored.
It is used to store information, and to convert input/output pulse trains accordingly.

For example, if there is a defect in a part of the storage loop 4 of positive 3, and for the sake of simplicity, the written or read information is all "1", then in the case of information writing, as shown in FIG. , clock C
The input signal pulse train synchronized with L is as shown in FIG. 4a.

However, since the storage loop 4 of No. 3, in which the third bit should be written, is defective, the pulse train must be as shown in FIG. 4.

Therefore, in the pulse train conversion circuit, the third and subsequent bits only need to be delayed by one clock based on the information from the defective loop memory circuit LNM.

In addition, in the case of reading, the output of the sense circuit SS changes as shown in Fig. 4. Since the information from the storage loop 4 of 3 is missing, the first and second bits are read for one clock. This means that the pulse train can be converted into a pulse train as shown in FIG.

Figure 5 shows an example of a pulse train conversion circuit PTC.
FFI, FF2 are flip-flops, ND1 to ND3 are NAND circuits, NR is a NOR circuit, CL is a clock, csl
, cs2 are control signals.

In the case of reading, the control signal C82 is applied to the NAND circuit ND3 for the bits before the defective loop and delayed by one clock by taking out the output of the flip-flop FF2, and the control signal C81 is applied to the bits after the defective loop. By taking out the output of the flip-flop FF1 in addition to the NAND circuit ND2, a pulse train as shown in FIG. 4C is obtained.

In the case of writing, the control signal C51 is applied to the NAND circuit ND2 for the bit before the defective loop, the output of the flip-flop FFl is taken out, and the control signal C32 is applied to the NAND circuit ND3 for the bit after the defective loop, and the output of the flip-flop FF1 is applied to the bit before the defective loop. By extracting the output of FF2, a pulse train as shown in FIG. 4 is obtained.

FIG. 6 shows an embodiment in which the pulse train shown in FIG. 5 is converted by a propagation bus line. Assuming that the magnetic domain moves in the direction of the arrow along the propagation bus line 6, a gate circuit is installed on the detector 7 side. 9 and a delay circuit 10 are provided, and a gate circuit 11 and a high-speed transmission circuit 12 are provided on the write/erase device 8 side.

Assuming that the storage loop 4 of No. 3 is defective as in the previous case, in the case of reading, the magnetic domains stored in the storage loops 4 of No. 1 and No. 2 are induced by the propagation bus 6. When the gate circuit 9 is reached, the gate circuit 9 is closed and the signal passes through the delay circuit 10 to delay the signal by one clock.
For the magnetic domains accumulated in the accumulation loop 4 after No. 4, the gate circuit 9 is opened and the magnetic domains are guided to the detector 7 as usual.

Therefore, the pulse train read out by the detector 7 is as shown in FIG. 4C.

In addition, in the case of writing, for the first and second bits, the gate circuit 11 is closed and the high-speed transmission circuit 12 is induced to accelerate by l clocks, and for the third and subsequent bits, the gate circuit 11 is opened and the normal propagation bus is used. 6.

Therefore, the pulse train is converted into the pulse train shown in FIG. 4, and the information regarding the defective loop is always 440 tt.

Such gate circuits 9 and 11 are controlled by the defective loop memory circuit LNM and the control circuit C in the same way as in FIG.
This is done using C.

That is, the gate circuits 9 and 11, the flame spread circuit 1°, and the high-speed transmission circuit 12 constitute a pulse train conversion circuit.

Of course, the arrangement of the high-speed transmission circuit 12 and the delay circuit 10 is not limited to the embodiment. For example, it is possible to replace the high-speed transmission circuit 12 and the delay circuit 10 in FIG. , 11 may be changed.

That is, in reading, the information of the accumulation loop before the defective loop is transmitted in the same way as usual, the information of the accumulation loop after the defective loop is accelerated by one clock by the high-speed transmission circuit 12, and in the case of writing, the information of the accumulation loop before the defective loop is transmitted as usual. It is sufficient to transmit the information in the same manner as usual, and control the gate circuits 9 and 11 based on the information in the defective loop memory circuit LMN so that the information of the bits after the defective bit is delayed by one clock by the delay circuit 10.

FIG. 7 shows an example of the aforementioned delay circuit 10, in which T,
■It is composed of a par pattern and a coil 13, and normally no current flows through the coil 13, so the magnetic domain 2 is a-+b→C→d→e→f→g→h→i→j→ It moves along the path due to the rotating magnetic field, but when a current is applied to the coil 13 when the magnetic domain 2 reaches point d, the magnetic field moves the magnetic domain 2 to point e', and the subsequent rotating magnetic field moves it to e'
-of'→〆→h'→i'→j'→ni'→l'→1-4
It moves along the path j→, and is delayed by exactly one cycle of the rotating magnetic field at point i.

FIG. 8 shows an example of the above-mentioned high-speed transmission circuit 12. Normally, since no current flows through the coil 14,
Magnetic domain 2 moves along the path a4b4C→-m−+ n→O→p→q.

When this magnetic domain 2 reaches point b, when a current is passed through the coil 14, the magnetic domain 2 moves from point b to point e', and then due to the rotating magnetic field, C'→d'→e'→f ' → end, and reaches the compressor circuit 15.

This compressor circuit 15 has a magnetic domain between each par pattern, and when the magnetic domain 2 reaches one point,
The magnetic domain in the compressor circuit 15 is pushed out to the right, and the pushed out magnetic domain is h'→i'→j'→Q+
It will move along a path of p − + q, and will be accelerated by exactly one cycle of the rotating magnetic field.

Although the embodiments described above are for cases where there is one defective loop, the present invention can also be applied to cases where there are more defective loops.
For example, in the embodiment shown in FIG. 5, 70 flips are further added and gate control is performed to delay the number of clocks for the number of defective loops and control the bit interval for the defective loops. You can also
In the embodiment shown in FIG. 8 and FIG. 8, it is sufficient to connect the number of defective loops in cascade.

Therefore, according to the present invention, even if a defective part occurs due to manufacturing a large magnetic thin plate, by forming a preliminary loop, it is possible to replace the defective loop with the defective part, and the pulse train can be replaced by the defective part. Conversion can also be performed by peripheral circuitry or a propagation bus, and in particular the latter can be performed by adding a few patterns, resulting in a very economical construction as well as a substantial improvement in the yield of magnetic thin plates as described above.

In the present invention, as mentioned above, the information for the defective loop is always set to "0" to prevent the cylindrical magnetic domain from being transferred to the defective loop. does not cause any undesirable behavior.

Specifically speaking, this is most noticeable if the defective loop contains a defect that cannot reliably hold the cylindrical magnetic domain and causes it to derail from the storage loop in the middle of the cycle; A large number of cylindrical magnetic domains floating in the magnetic thin plate are generated and invade the nearby storage loop and change the stored information, or they repel other cylindrical magnetic domains in the nearby storage loop and change their cylindrical shape. This derails the magnetic domain and also leads to changes in the stored information.

This problem is caused by the unique background of the cylindrical magnetic domain utilization device, which cannot provide a clear means of separation between the storage loops, and the present invention is capable of solving this problem very skillfully. can.

That is, according to the present invention, it is possible to prevent even the storage loops adjacent to the defective loop from causing defective operation.
This makes it possible to further improve the substantial yield of magnetic thin plates.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the principle of a magnetic storage device using cylindrical magnetic domains, Fig. 2 is an explanatory diagram of a conventional magnetic storage device, Fig. 3 is an explanatory diagram of an embodiment of the present invention, and Fig. 4 is an explanatory diagram of the conventional magnetic storage device. Operation explanatory diagram, 5th
The figure shows an example of the pulse train conversion circuit, FIG. 6 is an explanatory diagram of another embodiment of the present invention, FIG. 7 is an explanatory diagram of the configuration of the delay circuit, and FIG. 8 is an explanatory diagram of the configuration of the high-speed transmission circuit. . 1 is a magnetic thin plate, 2 is a cylindrical magnetic domain, 4 is a storage loop, 4a
is a preliminary loop, 5 is a gate circuit, 6 is a propagation bus, 7 is a detector, 8 is a write/erase device, 9 and 11 are gate circuits, 10 is a delay circuit, 12 is a high-speed transmission circuit, and C is a pulse train conversion The circuit, LNM is a defective loop memory circuit, and CC is a control circuit.

Claims (1)

[Scope of utility model registration request] comprising: a magnetic thin plate having an axis of easy magnetization perpendicular to the thin plate surface; and means for applying a bias magnetic field in the direction of the easy magnetization axis and a rotating magnetic field rotating within the thin plate surface to the magnetic thin plate; , a plurality of storage loops in which cylindrical magnetic domains generated by the bias magnetic field circulate by the rotating magnetic field, and a propagation bus that is commonly connected to the plurality of storage loops and transfers the plurality of cylindrical magnetic domains in series by the rotating magnetic field. and,
writing means for writing cylindrical magnetic domains in series on the propagation bus; detection means for detecting the cylindrical magnetic domains on the propagation bus; and writing means for writing cylindrical magnetic domains in series on the propagation bus; A magnetic storage device comprising a gate means for transferring magnetic domains into and out in a single space, a reserve loop commonly connected to the plurality of storage loops to the propagation bus via the gate means, and the storage loop. and a bad loop storage circuit that stores the position of the bad loop among the spare loops, the bad loop storage circuit, and a cylindrical magnetic domain that constitutes continuous write information during writing based on the contents of the bad loop storage circuit. The writing of the cylindrical magnetic domain to be transferred to each storage loop at a position that does not exceed the defective loop in the group or the serial transfer on the propagation bus is synchronized with the rotating magnetic field and delayed for a predetermined time, and at the time of takeover. A magnetic storage device characterized by comprising a pulse train conversion circuit that thins out read information corresponding to a defective loop position to narrow the array of continuously read information, so that cylindrical magnetic domains are always prevented from transferring to the defective loop.