JPH01149285A - Magnetic thin film storage element - Google Patents

Magnetic thin film storage element

Info

Publication number
JPH01149285A
JPH01149285A JP30598787A JP30598787A JPH01149285A JP H01149285 A JPH01149285 A JP H01149285A JP 30598787 A JP30598787 A JP 30598787A JP 30598787 A JP30598787 A JP 30598787A JP H01149285 A JPH01149285 A JP H01149285A
Authority
JP
Japan
Prior art keywords
thin film
memory
magnetic thin
film core
magnetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30598787A
Other languages
Japanese (ja)
Inventor
Hiroshi Akai
寛 赤井
Seiji Kishimoto
清治 岸本
Hiroaki Ono
裕明 小野
Nobuo Arai
信夫 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP30598787A priority Critical patent/JPH01149285A/en
Publication of JPH01149285A publication Critical patent/JPH01149285A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve storing density by causing the magnetizing condition of a magnetic thin film element to be single domain structure not to have magnetic wall structure. CONSTITUTION:A thin film core 3, which is one cell (= one bit corresponding) of a thin film core memory is caused to be the single domain structure. Thus, since this thin film core 3 does not have magnetic block structure in the core 3, the conventional close arrangement of the memory cell or a creep phenomenon, which is a problem in the general thin film core memory as malfunction in a memory condition due to high speed operation, does not completely appear. Accordingly, the memory cell can be closed. Thus, the storing density is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、記憶素子に係り、特に高密度記憶再生に好適
な素子構造を有する磁性薄膜記憶素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory element, and particularly to a magnetic thin film memory element having an element structure suitable for high-density storage and reproduction.

〔従来の技術〕[Conventional technology]

基板上に薄膜形成技術で多数の閉磁路構造を形成して成
る磁性薄膜記憶素子が提案されている。
A magnetic thin film memory element has been proposed in which a large number of closed magnetic circuit structures are formed on a substrate using a thin film formation technique.

従来のこの種の磁性薄膜記憶素子(以下、薄膜コアメモ
リと称する)としては、特公昭47−31854号公報
に記載のように桁線に連続的に磁性薄膜を形成したもの
や、特公昭4 B −28811号公報に記載のように
メモリ素子を1ビツトごとに分離した構造のものが知ら
れている。
Conventional magnetic thin film memory elements of this type (hereinafter referred to as thin film core memories) include those in which a magnetic thin film is continuously formed on the digit lines as described in Japanese Patent Publication No. 47-31854, As described in Japanese Patent No. B-28811, a structure in which memory elements are separated for each bit is known.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術においては、クリープ現象などによる記憶
内容の誤反転等によるメモリの信頬性低下を防ぐ為、1
ビツトに相当する記憶セルが数100μd〜数鶴2の大
きさになってしまい、記憶素子の高密度化に対応できな
いという問題があった。
In the above-mentioned conventional technology, in order to prevent the reliability of the memory from decreasing due to erroneous reversal of the memory contents due to the creep phenomenon, etc.
The size of a memory cell corresponding to a bit is several 100 micrometers to several square meters, and there is a problem in that it cannot cope with higher density storage elements.

また、誤反転等に対する信頼性も完璧なものではなかっ
た。
Furthermore, reliability against erroneous reversal and the like was not perfect.

本発明は、上記従来技術におけるメモリ内の記憶内容の
誤反転をなくし、メモリセルを近接させて高密度化を可
能とした磁性薄膜記憶素子を提供することを目的とする
SUMMARY OF THE INVENTION An object of the present invention is to provide a magnetic thin film memory element that eliminates the erroneous reversal of stored contents in a memory in the prior art and enables higher density by bringing memory cells closer together.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、薄膜コアメモリの1セル(=1ビット相当
)である薄膜コアを、磁壁を持たない、いわゆるシング
ルドメイン構造とすることにより、達成される。
The above object is achieved by making the thin film core, which is one cell (=corresponding to one bit) of the thin film core memory, have a so-called single domain structure without a domain wall.

〔作用〕[Effect]

シングルドメイン薄膜コアは、コア内に磁区構造を持た
ない。この為、クリープ現象等による記憶内容の誤反転
は皆無である。
A single domain thin film core has no magnetic domain structure within the core. Therefore, there is no erroneous reversal of stored contents due to creep phenomena or the like.

これによって、薄膜コアメモリの信頼性を大幅に向上で
きる。また、メモリセルを近接させることが可能となる
ので、記憶密度を格段に向上させることが可能となる。
This can greatly improve the reliability of thin film core memory. Furthermore, since it becomes possible to arrange the memory cells close to each other, it becomes possible to significantly improve the storage density.

〔実施例〕〔Example〕

以下、本発明の実施例を図を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明による薄膜コアメモリの一実施例を説明
いする1セル(1ビツト)の構成図であって、1は非磁
性のガラス基板、2.4はCug着膜をパターニングし
て形成した一対の導電線で、本実施例では、3は語線(
駆動線)、4は桁線(出力線)として用いる。3はパー
マロイ蒸着膜をパターニングして形成した薄膜コアで、
導電線2(語線)と平行に磁化容易軸を持たせている。
FIG. 1 is a configuration diagram of one cell (one bit) explaining one embodiment of a thin film core memory according to the present invention, in which 1 is a non-magnetic glass substrate, 2.4 is a patterned CUG film. In this example, 3 is a word line (
(drive line), 4 is used as a digit line (output line). 3 is a thin film core formed by patterning a permalloy vapor deposited film,
It has an axis of easy magnetization parallel to the conductive line 2 (word line).

また薄膜コアは、その内部に磁区を持たない、いわゆる
シングルドメイン構造に形成されており、形状として、
磁区を形成しにくい円形状としている。
In addition, the thin film core has a so-called single domain structure with no magnetic domain inside it, and its shape is as follows:
It has a circular shape that makes it difficult to form magnetic domains.

次に、本実施例のコアメモリの動作について説明する。Next, the operation of the core memory of this embodiment will be explained.

まず、薄膜コア3は、磁化容易軸に平行にn 1 tt
+t Ottのどちらかを向いた磁化状態で安定し、情
報の記憶状態に対応している(図では上向き、°′0′
″状態)。
First, the thin film core 3 has n 1 tt parallel to the axis of easy magnetization.
It is stable in a magnetized state facing either +t Ott, and corresponds to the information storage state (in the figure, upward, °'0'
"situation).

いま、語線2に誘電流■。を流すと、語線上のメモリ素
子3には、■8により発生した磁場Hwが作用し、メモ
リ素子3の磁化は、困難磁化方向に向かって回転する。
Now, there is an induced current ■ in word line 2. , the magnetic field Hw generated by (8) acts on the memory element 3 on the word line, and the magnetization of the memory element 3 rotates toward the difficult magnetization direction.

このとき、磁化がtt 1 ttの状態から回転したか
、n Onの状態から回転したかによって、桁&’j1
4には異なる極性のパルス電圧P4が誘起する。これが
、読み出し電圧となる。
At this time, depending on whether the magnetization rotates from the tt 1 tt state or from the n On state, the digit &'j1
4, a pulse voltage P4 of a different polarity is induced. This becomes the read voltage.

書き込みの場合には、磁化を困難軸に向けた状態におい
て、情報信号に対応する極性のパルス電流Idを桁線4
に流す。すると、パルスに対応した極性の磁場H4の作
用により、磁化の回転方向が決定され、u 1 tt又
はO゛′の容易軸方向の磁化状態に安定して、書き込み
完了となる(図ではfl I Itになる)。
In the case of writing, with the magnetization directed toward the difficult axis, a pulse current Id with a polarity corresponding to the information signal is applied to the digit line 4.
flow to. Then, due to the action of the magnetic field H4 with the polarity corresponding to the pulse, the rotational direction of magnetization is determined, and the magnetization state is stabilized in the easy axis direction of u 1 tt or O゛', and writing is completed (in the figure, fl I It becomes).

第2図は第1図に示したメモリセルを集積した構成例を
示す模式図であって、第1図と同一部分には同一符号を
付し、5は信号処理回路である。
FIG. 2 is a schematic diagram showing an example of a configuration in which the memory cells shown in FIG. 1 are integrated, and the same parts as in FIG. 1 are given the same reference numerals, and 5 is a signal processing circuit.

同図に示すように、実際の薄膜コアメモリでは、多数の
メモリセルを集積して構成され、大容量を実現する。こ
のとき、大容量セルに対応して引き出されている導電線
列(語線、桁線)の信号処理は、LSI等の信号処理回
路5によって行なわれる。このとき、第11図に示した
ごとく、薄膜コアをシングルドメイン構造にすることに
よって、これまでメモリセルの近接配置や、高速動作に
よるメモリー状態の誤動作として、一般の薄膜コアメモ
リで問題となっていたクリープ現象は全く発現せず、メ
モリの信頼性を大幅に向上させることができる。
As shown in the figure, an actual thin-film core memory is constructed by integrating a large number of memory cells to achieve a large capacity. At this time, signal processing of the conductive line arrays (word lines, digit lines) drawn out corresponding to the large capacity cells is performed by a signal processing circuit 5 such as an LSI. At this time, as shown in Figure 11, by making the thin-film core a single-domain structure, problems that have arisen in general thin-film core memories such as memory cell placement in close proximity and memory state malfunction due to high-speed operation have been solved. The creep phenomenon does not occur at all, and the reliability of the memory can be greatly improved.

また、シングルドメイン構造コアとして、薄膜コアの大
きさを数μdに小さくできるため、従来のコアメモリー
に対し、約500倍の高密度化を達成することが可能で
ある。
In addition, since the size of the thin film core can be reduced to several micrometers as a core with a single domain structure, it is possible to achieve a density approximately 500 times higher than that of a conventional core memory.

以上説明した実施例では、導電性、薄膜コア共に蒸着膜
のパターニングにより形成したが、膜形成は、スパッタ
リング、CVD等でも良く、また、パターニングも、イ
オンミリング等のドライエツチング、又はウェットエツ
チングでも良い。
In the embodiments described above, both the conductivity and the thin film core were formed by patterning the vapor deposited film, but the film formation may be performed by sputtering, CVD, etc., and the patterning may also be performed by dry etching such as ion milling, or wet etching. .

さらに、導電線、薄膜コアパターンを得る手段として、
パターンを印刷しても良い。この場合、量産性が格段に
向上する利点がある。
Furthermore, as a means to obtain conductive wires and thin film core patterns,
A pattern may also be printed. In this case, there is an advantage that mass productivity is greatly improved.

上記第1図の実施例では、メモリセルが、導電線(語線
)2−薄膜コア3−導電線(桁線)4の順で構成されて
いるが、語線2と桁線4の位置は逆にしてもよい。
In the embodiment shown in FIG. 1 above, the memory cell is constructed in the order of conductive line (word line) 2 - thin film core 3 - conductive line (digit line) 4. may be reversed.

第3図は本発明の他の実施例を説明するメモリセルの構
成図であって、第1図と同一符号は同一部分に対応する
FIG. 3 is a block diagram of a memory cell explaining another embodiment of the present invention, and the same reference numerals as in FIG. 1 correspond to the same parts.

同図においては、(a)に示すように、メモリセルの構
造を、薄膜コア3−導電線(語線)2−導電線(桁線)
4の順で基板1上に形成している。
In the figure, as shown in (a), the structure of the memory cell is shown as follows: thin film core 3 - conductive line (word line) 2 - conductive line (digit line)
4 are formed on the substrate 1 in this order.

また、同図(b)では、導電線(語線)2→導電線(桁
線)4−薄膜コア3の順で基板1上に形成している。
Further, in FIG. 2B, conductive lines (word lines) 2 -> conductive lines (digit lines) 4 - thin film cores 3 are formed on the substrate 1 in this order.

第4図は本発明のさらに他の実施例を説明するメモリセ
ルの構成図であって、長軸長と短軸長の異なる円形状と
したものであり、第1図、第3図と同一符号は同一部分
に対応する。
FIG. 4 is a configuration diagram of a memory cell explaining still another embodiment of the present invention, which has a circular shape with different major and minor axis lengths, and is the same as FIGS. 1 and 3. The symbols correspond to the same parts.

同図(a)において、薄膜コア3の形状は、前記実施例
では円板形状であるのに対し、だ円形状としたものであ
り、同図(b)においては長円形状としたものである。
In the same figure (a), the shape of the thin film core 3 is an elliptical shape, whereas it is a disk shape in the above embodiment, and in the same figure (b), it is an elliptical shape. be.

この様にすることによって、薄膜コア3の長手方向(長
軸長方向)に容易軸となる形状異方性が発生する為、外
部磁場の影響を受けに(くなる利点がある。
By doing so, shape anisotropy with an easy axis occurs in the longitudinal direction (long axis direction) of the thin film core 3, which has the advantage of being less susceptible to the influence of external magnetic fields.

上記各実施例において、薄膜コアの材料として、パーマ
ロイを用いているが、CO系合金等のメタル材など他の
磁性材でも良い。
In each of the above embodiments, permalloy is used as the material for the thin film core, but other magnetic materials such as metal materials such as CO-based alloys may be used.

なお、語線に平行な磁化容易軸は、成膜時における磁場
印加又は、成膜後の磁場中熱処理等の方法によって付与
すれば良い。
Note that the axis of easy magnetization parallel to the word line may be imparted by applying a magnetic field during film formation or by heat treatment in a magnetic field after film formation.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、薄膜コアメモリ
の記憶内容の誤反転は皆無となるので、信顛性が大幅に
向上する。又、メモリセルを近接させる構成が可能とな
り、記憶密度を従来比500倍以上の高密度化ができ、
前記従来技術の欠点を除いて優れた機能の磁性薄膜記憶
素子を提供することができる。
As described above, according to the present invention, there is no erroneous reversal of the contents stored in the thin film core memory, so reliability is greatly improved. In addition, it is possible to arrange memory cells close to each other, increasing the storage density by more than 500 times compared to conventional technology.
It is possible to provide a magnetic thin film memory element with excellent functionality by eliminating the drawbacks of the prior art.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すメモリセルの構成図、
第2図は第1図に示したメモリセルを集積した構成例を
示す模式図、第3図(a)(b)は本発明の他の実施例
を示すメモリセルの構成図、第4図(a)(b)は本発
明のさらに他の実施例を示すメモリセルの構成図である
。 1・・・・・・基板、2・・・・・・導電線(語ta)
、3・・・・・・薄膜コア、4・・・・・・導電線(桁
線)、5・・・・・・信号処理回路。 第1図 第2図 第3 (a) (b)
FIG. 1 is a configuration diagram of a memory cell showing an embodiment of the present invention;
2 is a schematic diagram showing a configuration example in which the memory cells shown in FIG. 1 are integrated; FIGS. 3(a) and 3(b) are configuration diagrams of memory cells showing another embodiment of the present invention; (a) and (b) are configuration diagrams of a memory cell showing still another embodiment of the present invention. 1... Board, 2... Conductive wire (word ta)
, 3... Thin film core, 4... Conductive wire (digit line), 5... Signal processing circuit. Figure 1 Figure 2 Figure 3 (a) (b)

Claims (1)

【特許請求の範囲】 1、基板上に、直交する状態で2層に形成された1対の
導電線列とその交差点に磁性薄膜素子を配置して成る磁
性薄膜記憶素子において、当該磁性薄膜素子の磁化状態
が、磁壁構造を持たないシングルドメイン構造であるこ
とを特徴とする磁性薄膜記憶素子。 2、特許請求の範囲第1項に記載の磁性薄膜記憶素子に
おいて、当該磁性薄膜素子が、長軸長と短軸長の異なる
円形状であることを特徴とする磁性薄膜記憶素子。
[Scope of Claims] 1. A magnetic thin film memory element comprising a pair of conductive line arrays formed in two layers orthogonally on a substrate and a magnetic thin film element disposed at the intersection thereof; A magnetic thin film memory element characterized in that the magnetization state of is a single domain structure having no domain wall structure. 2. A magnetic thin film memory element according to claim 1, wherein the magnetic thin film element has a circular shape with a long axis length and a short axis length different from each other.
JP30598787A 1987-12-04 1987-12-04 Magnetic thin film storage element Pending JPH01149285A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30598787A JPH01149285A (en) 1987-12-04 1987-12-04 Magnetic thin film storage element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30598787A JPH01149285A (en) 1987-12-04 1987-12-04 Magnetic thin film storage element

Publications (1)

Publication Number Publication Date
JPH01149285A true JPH01149285A (en) 1989-06-12

Family

ID=17951706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30598787A Pending JPH01149285A (en) 1987-12-04 1987-12-04 Magnetic thin film storage element

Country Status (1)

Country Link
JP (1) JPH01149285A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001510613A (en) * 1997-02-05 2001-07-31 モトローラ・インコーポレイテッド MRAM with aligned magnetic vectors
JP2005535111A (en) * 2002-07-17 2005-11-17 フリースケール セミコンダクター インコーポレイテッド Multilevel MRAM with improved memory density

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001510613A (en) * 1997-02-05 2001-07-31 モトローラ・インコーポレイテッド MRAM with aligned magnetic vectors
JP2005535111A (en) * 2002-07-17 2005-11-17 フリースケール セミコンダクター インコーポレイテッド Multilevel MRAM with improved memory density

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