SU1471284A1 - Bistable flip-flop retaining data with power off - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in control complexes for automated control systems. The purpose of the invention is to increase the permissible duration of power interruption while maintaining speed. The device contains a bistable cell on the input and output transistors 1 and 2, the memory capacitor 3, the discharge transistor 4, the gate transistor 6, the reset bus 7, the information recording 8, the power 9 and the total 10. By introducing additional field-effect transistor 5 and bipolar The transistor 14, controlled by the information recording signal, is recharged by the memory capacitor by an input signal parallel to the trigger switching, which improves the speed at the same allowable power interruption or increases the allowed duration of reryva power. 1 il.

Description

The invention relates to automation and computer technology and can be used in control systems for automated control systems.

The aim of the invention is to expand the scope by increasing the allowable duration of a power outage while maintaining performance and increase performance with the same allowable duration of a power outage.

The drawing shows an electrical schematic diagram of a device.

The two-stable trigger, which stores information when the power is turned off, contains a bistable cell on the input transistor 1 and the output transistor 2, a memory capacitor 3, a bit transistor 4, an additional field-effect transistor 5 in the communication circuit, a shutdown transistor 6, a reset bus 7, write information 8, power 9 and total 10; the first 11, second 12, third 13 resistors and an additional bipolar transistor 14.

A two-stable trigger that stores information when a power is turned off works as follows.

After turning on the supply voltage, the additional field-effect transistor 5 is open, providing a galvanic connection of the memory capacitor 3 with the gate of the input transistor 1 of the trigger. When a pulse is applied to the reset bus 7, the output transistor 2 of the trigger and the discharge transistor 4 are unlocked, so that the trigger is put into a state of logical 0, and the memory capacitor 3 is discharged. After the end of the reset pulse, the discharge transistor 4 is turned off, and the output transistor 2 remains open.

In the case of applying a pulse via the information recording bus 8, the input transistor 1 and the additional bipolar transistor 14 are unlocked, which, in turn, unlocks the shut-off transistor 6 through the second resistor 12, which is normally closed due to the presence of the first resistor 11. In this case, the memory capacitor 3 quickly charges through a gate transistor 6 (and a small resistance in the collector circuit, shown in dotted lines with a dash, the value of which is determined by the permissible current through the gate transistor 6). After the pulse of information recording, the additional bipolar transistor 14 and the gate transistor 6 are locked.

In the event of a power failure, the additional field-effect transistor 5 is locked and, since the transistors 4, 6, and 14 are locked, the voltage on the memory capacitor remains equal to the voltage on the gate of the input transistor 1 at the time of shutdown (slowly decreasing as the capacitor discharges through the leakage resistance).

After restoration of the supply voltage (within the time during which the voltage across the capacitor 3 remains sufficient to unlock the input transistor 1), an additional field effect transistor 5 is immediately unlocked and the voltage across the memory capacitor 3 is applied to the input transistor gate via a third resistor 13 1, setting it (and, therefore, the entire trigger). In the state that was before the power failure.

Claims (1)

Claim A two-stable trigger that saves information when the power is turned off, containing a bistable cell consisting of input and output transistors, a memory capacitor, a discharge and a lock transistor, a write bus, a power reset and a common one, the first output of the memory capacitor is connected to a common bus, the second output to the gate collectors transistor and discharge transistor, the emitter of which is connected to a common bus, and the base to the reset bus, the base of the gate transistor through the first resistor is connected to the power bus, to the first and second inputs b a stable cell, respectively, write and reset buses are connected, characterized in that, in order to expand the scope by increasing the permissible duration of the power interruption while maintaining speed and increasing speed with the same permissible duration of the power interruption, fawn and bipolar transistors are additionally introduced into it, and the discharge transistor has the opposite type of conductivity 1471284, the emitter of the gate transistor connected to the power bus, and the base through the second resistor to the collector to an additional bipolar transistor, the emitter of which is connected to the common bus and the base to the write bus, the source of the additional field-effect transistor is connected to the second output of the memory capacitor, the gate to the power bus, and the drain through the third resistor to the first input of the bistable cell.