JPS62160557U - - Google Patents
Info
- Publication number
- JPS62160557U JPS62160557U JP1986048042U JP4804286U JPS62160557U JP S62160557 U JPS62160557 U JP S62160557U JP 1986048042 U JP1986048042 U JP 1986048042U JP 4804286 U JP4804286 U JP 4804286U JP S62160557 U JPS62160557 U JP S62160557U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- chip carrier
- thickness
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第1図は、本考案の一実施例の斜視図、第2図
は本考案の一実施例の断面図、第3図は積層構造
の斜視図、第4図は従来装置の一例の斜視図であ
る。 〈符号の説明〉、1……チツプキヤリア、2…
…半導体素子、3……ワイヤ、4……サブストレ
ート、5……側面電極、6……下部電極、7……
凹部、8……基板、9……第1のチツプキヤリア
、10……ハンダ、11……第2のチツプキヤリ
ア。
は本考案の一実施例の断面図、第3図は積層構造
の斜視図、第4図は従来装置の一例の斜視図であ
る。 〈符号の説明〉、1……チツプキヤリア、2…
…半導体素子、3……ワイヤ、4……サブストレ
ート、5……側面電極、6……下部電極、7……
凹部、8……基板、9……第1のチツプキヤリア
、10……ハンダ、11……第2のチツプキヤリ
ア。
Claims (1)
- 絶縁材料からなるサブストレートの表面に半導
体素子を固着し、上記サブストレートを基板に固
着し、上記サブストレートに設けた電極を介して
上記半導体素子と上記基板の電極とを接続するい
わゆるチツプキヤリア構造において、上記サブス
トレートの周辺部分の厚さを中央部分の厚さより
大きくして断面が凹型の形状とし、複数のサブス
トレートを基板上に積層して配置することを特徴
とするチツプキヤリア構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986048042U JPS62160557U (ja) | 1986-04-02 | 1986-04-02 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986048042U JPS62160557U (ja) | 1986-04-02 | 1986-04-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62160557U true JPS62160557U (ja) | 1987-10-13 |
Family
ID=30869207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986048042U Pending JPS62160557U (ja) | 1986-04-02 | 1986-04-02 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62160557U (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08213543A (ja) * | 1994-10-20 | 1996-08-20 | Hughes Aircraft Co | マルチダイパッケージ装置 |
KR101175227B1 (ko) | 2011-06-27 | 2012-08-21 | 매그나칩 반도체 유한회사 | 패키지 |
-
1986
- 1986-04-02 JP JP1986048042U patent/JPS62160557U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08213543A (ja) * | 1994-10-20 | 1996-08-20 | Hughes Aircraft Co | マルチダイパッケージ装置 |
KR101175227B1 (ko) | 2011-06-27 | 2012-08-21 | 매그나칩 반도체 유한회사 | 패키지 |