JPH01157433U - - Google Patents

Info

Publication number
JPH01157433U
JPH01157433U JP1988046333U JP4633388U JPH01157433U JP H01157433 U JPH01157433 U JP H01157433U JP 1988046333 U JP1988046333 U JP 1988046333U JP 4633388 U JP4633388 U JP 4633388U JP H01157433 U JPH01157433 U JP H01157433U
Authority
JP
Japan
Prior art keywords
bump electrode
semiconductor device
pattern
length measurement
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988046333U
Other languages
English (en)
Other versions
JPH0416425Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988046333U priority Critical patent/JPH0416425Y2/ja
Publication of JPH01157433U publication Critical patent/JPH01157433U/ja
Application granted granted Critical
Publication of JPH0416425Y2 publication Critical patent/JPH0416425Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】
第1図及び第2図は本考案の実施例を説明する
上面図、第3図は従来の実施例を説明する上面図
、第4図は一般的なバンプ電極の構造を説明する
断面図である。 1はパツド電極、2はバンプ電極、3は測長パ
ターン、4は最小のパターン、5は最大のパター
ンである。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 半導体基板の絶縁膜上に複数のパツド電極
    を設け前記パツド電極上にバンプ電極を形成する
    半導体装置において、前記パツド電極に隣接して
    前記バンプ電極の大きさをモニターする測長パタ
    ーンを設けることを特徴とするバンプ電極を有す
    る半導体装置。 (2) 前記測長パターンを最小のパターンと最大
    のパターンとより構成することを特徴とする請求
    項1記載のバンプ電極を有する半導体装置。
JP1988046333U 1988-04-06 1988-04-06 Expired JPH0416425Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988046333U JPH0416425Y2 (ja) 1988-04-06 1988-04-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988046333U JPH0416425Y2 (ja) 1988-04-06 1988-04-06

Publications (2)

Publication Number Publication Date
JPH01157433U true JPH01157433U (ja) 1989-10-30
JPH0416425Y2 JPH0416425Y2 (ja) 1992-04-13

Family

ID=31272604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988046333U Expired JPH0416425Y2 (ja) 1988-04-06 1988-04-06

Country Status (1)

Country Link
JP (1) JPH0416425Y2 (ja)

Also Published As

Publication number Publication date
JPH0416425Y2 (ja) 1992-04-13

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