JPS6215895B2 - - Google Patents

Info

Publication number
JPS6215895B2
JPS6215895B2 JP57203050A JP20305082A JPS6215895B2 JP S6215895 B2 JPS6215895 B2 JP S6215895B2 JP 57203050 A JP57203050 A JP 57203050A JP 20305082 A JP20305082 A JP 20305082A JP S6215895 B2 JPS6215895 B2 JP S6215895B2
Authority
JP
Japan
Prior art keywords
buffer storage
intermediate buffer
processing unit
move
channel processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57203050A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5994285A (ja
Inventor
Nobuhiko Kuribayashi
Takashi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57203050A priority Critical patent/JPS5994285A/ja
Publication of JPS5994285A publication Critical patent/JPS5994285A/ja
Publication of JPS6215895B2 publication Critical patent/JPS6215895B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP57203050A 1982-11-19 1982-11-19 中間バツフアストレ−ジ制御方式 Granted JPS5994285A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57203050A JPS5994285A (ja) 1982-11-19 1982-11-19 中間バツフアストレ−ジ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57203050A JPS5994285A (ja) 1982-11-19 1982-11-19 中間バツフアストレ−ジ制御方式

Publications (2)

Publication Number Publication Date
JPS5994285A JPS5994285A (ja) 1984-05-30
JPS6215895B2 true JPS6215895B2 (enrdf_load_stackoverflow) 1987-04-09

Family

ID=16467507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57203050A Granted JPS5994285A (ja) 1982-11-19 1982-11-19 中間バツフアストレ−ジ制御方式

Country Status (1)

Country Link
JP (1) JPS5994285A (enrdf_load_stackoverflow)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50141938A (enrdf_load_stackoverflow) * 1974-05-02 1975-11-15

Also Published As

Publication number Publication date
JPS5994285A (ja) 1984-05-30

Similar Documents

Publication Publication Date Title
JPS58102381A (ja) バツフアメモリ
JPS5898893A (ja) 情報処理装置
EP0533427B1 (en) Computer memory control system
JPS60124754A (ja) バッファ記憶制御装置
US4424564A (en) Data processing system providing dual storage of reference bits
JPH0548497B2 (enrdf_load_stackoverflow)
JPS6215895B2 (enrdf_load_stackoverflow)
JP2580263B2 (ja) バッファ記憶装置
KR920005296B1 (ko) 정보처리장치
JPS634356A (ja) デイスクキヤツシユ順次モ−ド共用処理方式
JP2703255B2 (ja) キャッシュメモリ書込み装置
JPS6252339B2 (enrdf_load_stackoverflow)
JPS6214919B2 (enrdf_load_stackoverflow)
JPH04288647A (ja) キャッシュメモリにおける置き換え制御装置
EP0400851A2 (en) Efficient cache utilizing a store buffer
JPH0526216B2 (enrdf_load_stackoverflow)
JPS6116348A (ja) バツフア・メモリ装置
JPS6063650A (ja) バッファメモリ一致制御方式
JPS60129860A (ja) アドレス指定例外検出方式
JPS63282544A (ja) ワンチツプキヤツシユメモリ
JPH04273549A (ja) キャッシュメモリのライトバック方式
JPH04156637A (ja) キャッシュメモリ制御方式
JPS583175A (ja) 仮想記憶制御装置
JPS5965358A (ja) メモリ・スワツプ時のリトライ制御方式
JPS6055454A (ja) デ−タ転送制御方式