JPS62158337A - Mounting structure of electronic parts and their mounting method - Google Patents

Mounting structure of electronic parts and their mounting method

Info

Publication number
JPS62158337A
JPS62158337A JP60298983A JP29898385A JPS62158337A JP S62158337 A JPS62158337 A JP S62158337A JP 60298983 A JP60298983 A JP 60298983A JP 29898385 A JP29898385 A JP 29898385A JP S62158337 A JPS62158337 A JP S62158337A
Authority
JP
Japan
Prior art keywords
electronic component
resin
resin film
electronic parts
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60298983A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yamamura
山村　信幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP60298983A priority Critical patent/JPS62158337A/en
Publication of JPS62158337A publication Critical patent/JPS62158337A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor

Abstract

PURPOSE:To simply and easily connect chip-type electronic parts with wiring patters, by forming contact holes at resinous films composed on a resinous substrate and besides providing the surface of the resinous films with the wiring patterns which are connected with the terminal electrodes of the chip-type electronic parts through the contact holes. CONSTITUTION:Contact holes 4a... are formed at appointed positions of resinous films 4, and electrode pads/terminals 3a and 3a in respective electronic parts 2 and 3 are made to be exposed outside. Then, a conductive thin film 5' is formed on a surface (an upper plane) of a resinous substrate 1 so that one part of the thin film 5' passes through the contact holes 4a... of the resinous films 4 to be in direct contact with the electrode pads/terminals 3a and 3a in the respective electronic parts 2 and 3 and to have continuity with them. And, the conductive thin film 5' is formed on prescribed wiring patterns 5 by photo-lithographic method. In this case, not only the patterns for drawing out the electrode pads/terminals 3a and 3a in the respective electronic parts 2 and 3, but also all of the wiring patterns are formed on the resinous films 4.

Description

【発明の詳細な説明】 ［発明の技術分野］ この発明は電子部品の実装構造およびその実装方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an electronic component mounting structure and a mounting method thereof.

［従来技術とその問題点］ 従来、チップ型電子部品、例えば半導体チップを配線基
板に１１ｉ続する方法としては、金、銅、アルミ等の金
属細線を半導体チップの表面に形成された電極パッド部
と配線基板の電極端子との間に張り渡して、熱圧着また
は超音波溶着等によって接続するワイヤ・ポンディング
法や、あるいは。[Prior art and its problems] Conventionally, as a method for connecting a chip-type electronic component, such as a semiconductor chip, to a wiring board, a thin metal wire of gold, copper, aluminum, etc. is connected to an electrode pad portion formed on the surface of the semiconductor chip. wire bonding method, in which the wire is stretched between the wire and the electrode terminal of the wiring board, and connected by thermocompression bonding or ultrasonic welding, or

予め半導体チップの電極パッドに対応させて配線基板上
に配線パターンを形成し、この配線パターン上に半導体
チップを配若し、一括してポンディングを行なうワイヤ
レス・ポンディング法等がある。There is a wireless bonding method in which a wiring pattern is formed in advance on a wiring board in correspondence with the electrode pads of a semiconductor chip, semiconductor chips are placed on this wiring pattern, and bonding is performed all at once.

しかしながら、上述したいずれの方法においても、大掛
かりなポンディング装置が必要であり。However, in any of the above-mentioned methods, a large-scale bonding device is required.

簡単に接続作業を行なうことができないという問題があ
る。しかも、このような方法では、接着時の機械的精度
および接着の機械的強度の保証等の点から半導体チップ
の電極パッドの大きさを一定面ａ（約５０ｇ、ｍ角）以
上にする必要があるため、半導体チップの面積の増大、
あるいは取り出し電極数に制限を生じる等の不都合があ
る。There is a problem that connection work cannot be easily performed. Moreover, in such a method, the size of the electrode pad of the semiconductor chip must be larger than a certain area a (approximately 50 g, m square) from the viewpoint of ensuring mechanical precision during bonding and mechanical strength of bonding. Due to the increase in the area of semiconductor chips,
Alternatively, there is a problem that the number of electrodes to be taken out is limited.

（発明の目的］ この発明は上記のような事情を考慮してなされたもので
、その目的とするところは、大掛かりなポンディング装
置を必要とせず、簡単かつ容易にチップ型電子部品と配
線パターンとを接続することができ、かつ電気的信頼性
の高い電子部品の実装構造およびその実装方法を提供す
ることにある。(Objective of the Invention) This invention was made in consideration of the above circumstances, and its purpose is to easily and easily connect chip-type electronic components and wiring patterns without requiring a large-scale bonding device. It is an object of the present invention to provide a mounting structure for electronic components that can be connected to the electronic components and has high electrical reliability, and a method for mounting the same.

［発明の要点］ この発明は上記のような目的を達成するために、チップ
型の電子部品をその端子電極形成面を露出させて樹脂基
板に埋め込み、この電子部品を被覆する樹脂膜を前記樹
脂基板上に設け、この樹脂膜にコンタクトホールを形成
すると共に、樹脂膜の表面にコンタクトホールを介して
前記電子部品の端子電極に接続される配線パターンを形
成するようにしたものである。[Summary of the Invention] In order to achieve the above object, the present invention embeds a chip-type electronic component in a resin substrate with its terminal electrode forming surface exposed, and a resin film covering the electronic component is coated with the resin. A contact hole is formed on the resin film on a substrate, and a wiring pattern is formed on the surface of the resin film to be connected to the terminal electrode of the electronic component through the contact hole.

［実施例］ 以下、第１図及び第２図を参照して、この発明の一実施
例を説明する。[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

第１図はチップ型電子部品の実装構造を示し。Figure 1 shows the mounting structure of a chip-type electronic component.

図中１は樹脂基板である。この樹脂基板ｌはエポキシ等
からなるシート状のものであり、この樹脂基板ｌにはＬ
ＳＩ等の半導体チップ２およびコンデンサチップ３等の
電子部品が埋め込まれている。４は樹脂基板１および電
子部品２．３の表面を被覆する樹脂膜で、この樹脂膜４
には前記電子部品２，３の電極部に対応する部分にコン
タクトホール４ａが形成されている。５は電子部品２．
３間の接続及びこれらの電子部品２．３と他の電子部品
との接続を行う配線パターン、６は保護膜である。In the figure, 1 is a resin substrate. This resin substrate l is a sheet-like material made of epoxy or the like.
Electronic components such as a semiconductor chip 2 such as SI and a capacitor chip 3 are embedded. 4 is a resin film that covers the surfaces of the resin substrate 1 and the electronic components 2.3;
A contact hole 4a is formed in a portion corresponding to the electrode portions of the electronic components 2 and 3. 5 is an electronic component 2.
A wiring pattern 6 is a protective film for connecting the electronic components 2 and 3 and connecting the electronic components 2 and 3 to other electronic components.

次に、第２図を参照して、その実装方法を説明する・ 第２図（ａ）は樹脂基板ｌを示す、この樹脂基板ｌはエ
ポキシ等からなる樹脂製のシートであり、その所定箇所
には凹部１ａ、ｌｂが形成されている。この凹部１ａ、
ｌｂ内には第２図（ｂ）に示すようにＬＳＩ等の半導体
チップ２およびチップコンデンサ３等の電子部品が設け
られ、モールドされる。即ち、まず凹部１ａ、ｌｂ内に
電子部品２，３を配置して接着した後、これら各電子部
品２．３をモールドスル樹ＩＦｔｌｌ！２４ヲ樹Ｉｒｉ
′１基板１上に厚さが２７ｚｍ程度の均一な面となるよ
うに塗布する。この場合、凹部１ａ、ｌｂと各電子部品
２．３との隙間を埋めるために、塗布する荊に、各電子
部品２．３を備えた樹脂基板ｌを減圧状態におき、感光
性ポリイミド等の樹脂を滴下して大気圧に戻して、上述
した隙間に樹脂液を染み込ませ、しかる後に樹脂基板ｌ
を回転させる０回転塗布法により感光性ポリイミド等か
らなる樹脂ｌＩ２４が樹脂基板ｌの上面全体に均一な膜
として形成される。Next, the mounting method will be explained with reference to Fig. 2. Fig. 2 (a) shows a resin board l. This resin board l is a resin sheet made of epoxy etc. Recesses 1a and lb are formed in the recesses 1a and lb. This recess 1a,
As shown in FIG. 2(b), electronic components such as a semiconductor chip 2 such as an LSI and a chip capacitor 3 are provided and molded in the inside. That is, first, the electronic components 2 and 3 are placed and bonded in the recesses 1a and 1b, and then the electronic components 2 and 3 are molded together. 24woki Iri
'1 Coating is applied onto the substrate 1 so as to form a uniform surface with a thickness of about 27 zm. In this case, in order to fill the gaps between the recesses 1a, lb and each electronic component 2.3, the resin substrate 1 provided with each electronic component 2.3 is placed in a reduced pressure state on the surface to be coated, and a material such as photosensitive polyimide is applied. Drop the resin, return it to atmospheric pressure, soak the resin liquid into the above-mentioned gap, and then attach the resin substrate l
A resin lI24 made of photosensitive polyimide or the like is formed as a uniform film over the entire upper surface of the resin substrate l by a zero rotation coating method in which the resin substrate l is rotated.

このように塗布された樹脂膜４にはフォト・マスク法或
いはフォト・リソグラフィ法を用いて第２図（Ｃ）に示
すように、半導体チップ２の電極パッド（図示せず）と
チップコンデンサ３の電極端子３ａ、３ａとに対応する
部分にコンタクトホール４ａ・・・を形成する０例えば
樹脂１漠４を感光性ポリイミドで形成されている場合に
は、フォト◆マスク法により樹脂膜４に光を照射して現
像するだけで良い、すると、樹脂膜４の所定箇所（つま
り、各°電子部品２．３の電極パッドおよび電極端子３
ａ、３ａに対応する部分）にコンタクトホール４　ａ＊
　参−が形成され、各電子部品の電極パッドおよび電極
端子３ａ、３ａが外部に露出する。The resin film 4 coated in this way is coated with the electrode pads (not shown) of the semiconductor chip 2 and the chip capacitor 3 using a photo mask method or a photolithography method, as shown in FIG. 2(C). Contact holes 4a are formed in portions corresponding to the electrode terminals 3a, 3a. For example, when the resin 1 and 4 are made of photosensitive polyimide, light is applied to the resin film 4 using a photo mask method. All you need to do is to irradiate and develop. Then, the resin film 4 can be exposed to predetermined locations (i.e., the electrode pads and electrode terminals 3 of each electronic component 2.3).
Contact hole 4 a*
The electrode pads and electrode terminals 3a, 3a of each electronic component are exposed to the outside.

この後、第２図（ｄ）に示すように、樹脂基板１の表面
（上面）に導電性薄膜５′を形成する。Thereafter, as shown in FIG. 2(d), a conductive thin film 5' is formed on the surface (upper surface) of the resin substrate 1.

この薄膜５°はアルミ等の全屈からなる薄い膜であり、
スパッタ法等により樹脂基板１の表面に厚さ２ｐｍ程度
に蒸着される。しかも、ｇＪ膜５′の一部は樹脂膜４の
コンタクトホール４ａ１１・０を通り、各電子部品２．
３の電極パッドおよび電極端子３ａ、３ａに直接接触し
て導通する。This thin film 5° is a thin film made of fully bent aluminum etc.
It is deposited to a thickness of about 2 pm on the surface of the resin substrate 1 by sputtering or the like. Moreover, a part of the gJ film 5' passes through the contact hole 4a11.0 of the resin film 4, and each electronic component 2.
It directly contacts the electrode pad No. 3 and the electrode terminals 3a, 3a for electrical conduction.

そして、導電性薄［５’をフォト・リソグラフィ法によ
って第２図（ｅ）に示すような所定の配線パターン５に
形成する。即ち、導電性薄ｗＪ５゜の上面にフォト・レ
ジスト膜を２ｇｍ程度の厚さに塗布し、フォト拳リソグ
ラフィ法により所定箇所の導電性薄膜５°をエツチング
することにより、所定の配線パターン５を形成する。こ
の場合には、各電子部品２，３の電極パッドおよび電極
端子３ａ、３ａを外部へ導くパターンだけでなく、全て
の配線パターンを樹脂膜４上に形成する。このように配
線パターン５が形成された樹脂基板１上には、第１図に
示すように、エポキシ樹脂等の保護膜６を塗布して、全
体を保護する。Then, a conductive thin layer [5' is formed into a predetermined wiring pattern 5 as shown in FIG. 2(e) by photolithography. That is, a photoresist film is applied to a thickness of about 2 gm on the upper surface of the conductive thin film wJ5°, and a predetermined wiring pattern 5 is formed by etching the conductive thin film at a predetermined location by photolithography. do. In this case, not only the patterns for guiding the electrode pads and electrode terminals 3a, 3a of each electronic component 2, 3 to the outside, but also all the wiring patterns are formed on the resin film 4. As shown in FIG. 1, a protective film 6 such as epoxy resin is coated on the resin substrate 1 on which the wiring pattern 5 is formed in this way to protect the entire surface.

上記のような電子部品の実装構造および実装方法によれ
ば、大掛かりなポンディング装置を必要とせず、極めて
簡単かつ容易に半導体チップ２およびチップコンデンサ
３と配線パターン５とを接続することができると共に、
かつ導通信頼性の高いものを得ることができる。この場
合、特に樹脂＋１’；Ｉ　４の表面が均一な平面に形成
され、しかもこの平面上に形成する配線パターン５をフ
ォト・リングラフィ法によって行うようにしたので、半
導体チップ２の電極パッドが１　ｇｍ角程度のもでも充
分に外部へ導くことができ、高密度の配線が可ｆｌとな
るばかりか、半導体チップ２の縮小、およびその電極の
高密度化等を図ることができる。According to the electronic component mounting structure and mounting method described above, it is possible to connect the semiconductor chip 2 and the chip capacitor 3 to the wiring pattern 5 extremely simply and easily without requiring a large-scale bonding device. ,
Moreover, it is possible to obtain a product with high conduction reliability. In this case, in particular, the surface of the resin +1'; Even a diameter of approximately 1 gm square can be sufficiently guided to the outside, and not only can high-density wiring be made flexible, but also the semiconductor chip 2 can be reduced in size and its electrodes can be densely packed.

なお、上記実施例では、樹脂基板ｌに予め凹部１ａ、１
ｂを形成し、そこに電子部品を埋め込むようにしたが、
樹脂基板ｌを熱可塑性の樹脂で構成し、電子部品を加熱
圧入するようにしても良い、即ち、第３図（ａ）に示す
ように、ポリエチレン・テレフタレート等からなる熱可
塑性の樹脂基板１１に反導体チップ１２およびコンデン
サチップ１３等の電子部品を加熱圧入し、リフローして
樹脂基板１１の表面を平担化した後、同図（ｂ）に示す
ように感光性ポリイミド等の樹脂膜１４を形成し、しか
る後に第２図（Ｃ）乃至（ｅ）に示した工程で製造する
ようにしても良い、更に、この発明は上述した実施例に
限定されることなく、その主旨を逸脱しない範囲内にお
いて種々変形応用可能である。In the above embodiment, the recesses 1a, 1 are formed in advance in the resin substrate l.
b and embedded electronic components there, but
The resin substrate 1 may be made of a thermoplastic resin, and the electronic components may be heated and press-fitted into the resin substrate 11 made of polyethylene terephthalate or the like, as shown in FIG. 3(a). After heating and press-fitting electronic components such as the anti-conductor chip 12 and the capacitor chip 13, and flattening the surface of the resin substrate 11 by reflowing, a resin film 14 made of photosensitive polyimide or the like is coated as shown in FIG. The present invention is not limited to the above-described embodiments, and may be manufactured within the scope of the invention without departing from the spirit thereof. Various modifications and applications are possible within the scope.

［発明の効果］ 以上説明したように、この発明はチップ型の電子部品を
その端子電極形成面を露出させて樹脂基板に埋め込みこ
の電子部品を被覆する樹脂膜を前記樹脂基板上に設け、
この樹脂膜にコンタクトホールを形成すると共に、樹脂
膜の表面にコンタクトホールを介して前記電子部品の端
子電極に接続される配線パターンを形成するようにした
ので、大掛かりなポンディング装置を必要とせず、簡単
かつ容易にチップ型電子部品と配線パターンとを接続す
ることができ、かつ電気的信頼性の高いものを得ること
ができる。[Effects of the Invention] As explained above, the present invention embeds a chip-type electronic component in a resin substrate with its terminal electrode forming surface exposed, and provides a resin film covering the electronic component on the resin substrate,
A contact hole is formed in this resin film, and a wiring pattern is formed on the surface of the resin film to be connected to the terminal electrode of the electronic component via the contact hole, so there is no need for a large-scale bonding device. , it is possible to simply and easily connect a chip-type electronic component and a wiring pattern, and it is possible to obtain a device with high electrical reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例を示す構造図、第２図はそ
の工程図、第３図は他の実施例を示す実装工程図である
。 ■・・・・・・樹脂基板、１ａ・・・・・・凹部、２・
・・・・・半導体チップ、３・・・・・・チップコンデ
ンサ、３ａ・・・・・・電極端子、４・・・・・・樹脂
膜、４ａ・・・・・・コンタクトホール、５・・・・・
・配線パターン。 手続補正書（自発） 昭和６１年１月２９日FIG. 1 is a structural diagram showing one embodiment of the present invention, FIG. 2 is a process diagram thereof, and FIG. 3 is a mounting process diagram showing another embodiment. ■... Resin substrate, 1a... Concavity, 2.
... Semiconductor chip, 3 ... Chip capacitor, 3a ... Electrode terminal, 4 ... Resin film, 4a ... Contact hole, 5.・・・・・・
・Wiring pattern. Procedural amendment (voluntary) January 29, 1985

Claims (2)

【特許請求の範囲】[Claims] （１）チップ型の電子部品を配線基板に実装する電子部
品の実装構造に於て、前記配線基板は樹脂基板とこの樹
脂基板の表面を被覆する樹脂膜とこの樹脂膜上に形成さ
れた配線パターンとからなり、前記電子部品はその端子
電極形成面を前記樹脂膜に密着させた状態で前記樹脂基
板中に埋め込まれ、且つその端子電極は前記樹脂膜に形
成されたコンタクトホールを介して前記配線パターンと
直接接続されていることを特徴とする電子部品の実装構
造。(1) In an electronic component mounting structure in which a chip-type electronic component is mounted on a wiring board, the wiring board includes a resin board, a resin film covering the surface of the resin board, and wiring formed on the resin film. The electronic component is embedded in the resin substrate with its terminal electrode forming surface in close contact with the resin film, and the terminal electrode is connected to the resin film through a contact hole formed in the resin film. An electronic component mounting structure characterized by being directly connected to a wiring pattern. （２）チップ型の電子部品を配線基板に実装する電子部
品の実装方法に於て、前記電子部品をその端子電極形成
面を露出させて樹脂基板に埋め込む工程と、この樹脂基
板の表面及び前記電子部品の端子電極形成面を一体的に
被覆する樹脂膜を形成する工程と、この樹脂膜の前記電
子部品の端子電極に対応する部分にコンタクトホールを
形成する工程と、前記樹脂膜の表面にコンタクトホール
を介して前記電子部品の端子電極に接続される配線パタ
ーンを形成する工程とからなる電子部品の実装方法。(2) In the electronic component mounting method of mounting a chip-type electronic component on a wiring board, the electronic component is embedded in a resin substrate with its terminal electrode forming surface exposed, and the surface of the resin substrate and the a step of forming a resin film that integrally covers the terminal electrode formation surface of the electronic component; a step of forming a contact hole in a portion of the resin film corresponding to the terminal electrode of the electronic component; and a step of forming a contact hole on the surface of the resin film. A method for mounting an electronic component, comprising the step of forming a wiring pattern connected to a terminal electrode of the electronic component via a contact hole.
JP60298983A 1985-12-31 1985-12-31 Mounting structure of electronic parts and their mounting method Pending JPS62158337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60298983A JPS62158337A (en) 1985-12-31 1985-12-31 Mounting structure of electronic parts and their mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60298983A JPS62158337A (en) 1985-12-31 1985-12-31 Mounting structure of electronic parts and their mounting method

Publications (1)

Publication Number Publication Date
JPS62158337A true JPS62158337A (en) 1987-07-14

Family

ID=17866714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60298983A Pending JPS62158337A (en) 1985-12-31 1985-12-31 Mounting structure of electronic parts and their mounting method

Country Status (1)

Country Link
JP (1) JPS62158337A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system

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