JPS62158336A - Mounting structure of electronic parts and their mounting method - Google Patents

Mounting structure of electronic parts and their mounting method

Info

Publication number
JPS62158336A
JPS62158336A JP60298982A JP29898285A JPS62158336A JP S62158336 A JPS62158336 A JP S62158336A JP 60298982 A JP60298982 A JP 60298982A JP 29898285 A JP29898285 A JP 29898285A JP S62158336 A JPS62158336 A JP S62158336A
Authority
JP
Japan
Prior art keywords
chip
electronic component
resin substrate
thin film
wiring patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60298982A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yamamura
山村 信幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP60298982A priority Critical patent/JPS62158336A/en
Publication of JPS62158336A publication Critical patent/JPS62158336A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor

Abstract

PURPOSE:To simply and easily connect chip-type electronic parts with wiring patterns, by forming contact holes at thin film parts in a resinous substrate and then forming wiring patterns which are connected with terminal electrodes of chip-type electronic parts through the contact holes on the surface of the resinous substrate. CONSTITUTION:Contact holes 4a... are formed by an etching process on thin films 4, which are parts included in a resinous substrate 1, and at the positions corresponding to electrode pads on a semiconductor chip 2 and electrode terminals 3a on a capacitor chip 3. Wiring patterns 5... are formed on the upper surface of the resinous substrate 1 by the etching resinous substrate 1. Partial wiring patterns are directly connected with respectively the electrode pads on the semiconductor chip 2 and the electrode terminals 3a on the capacitor chip 3. Hence, the chip-type electronic parts can be simply and easily connected with the wiring patterns without requiring a large-scale bonding apparatus.

Description

【発明の詳細な説明】 [発明の技術分野] この%Ijlは電子部品の実装構造およびその実装方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] This %Ijl relates to an electronic component mounting structure and its mounting method.

[従来技術とその間通点] 従来、チップJ!!電子部品1例えば半導体チップを配
線基板に接続する方法としては、金、銅、アルミ等の金
属細線を半導体チップの表面に形成された電極パッド部
と配!a基板の電極端子との間に張り渡して、熱圧着ま
たは超音波岩石等によって接続するワイヤ・ポンディン
グ法や、あるいは。
[Conventional technology and common points] Conventionally, Chip J! ! Electronic component 1 For example, a method for connecting a semiconductor chip to a wiring board is to connect thin metal wires of gold, copper, aluminum, etc. to electrode pads formed on the surface of the semiconductor chip. a Wire bonding method, in which the wire is stretched between the electrode terminals of the substrate and connected by thermocompression bonding or ultrasonic rock, or the like.

予め半導体チップの電極パッドに対応させて配線基板上
に配線パターンを形成し、この配線パターン上に半導体
チップを配置し、一括してポンディングを行なうワイヤ
レス・ポンディング法等がある。
There is a wireless bonding method in which a wiring pattern is formed in advance on a wiring board in correspondence with the electrode pads of a semiconductor chip, semiconductor chips are placed on this wiring pattern, and bonding is performed all at once.

しかしながら、上述したいずれの方法においても、大掛
かりなポンディング装置が必要であり、簡単に接続作業
を行なうことができないという問題がある。しかも、こ
のような方法では、接着時の機械的精度および接着の機
械的強度の保証等の点から半導体チップの電極パッドの
大きさを一定面積(約501Lm角)以上にする必要が
あるため、半導体チップの面積の増大、あるいは取り出
し電極数に制限を生じる等の不都合がある。
However, in any of the above-mentioned methods, a large-scale bonding device is required, and there is a problem in that the connection work cannot be easily performed. Moreover, in such a method, the size of the electrode pad of the semiconductor chip must be larger than a certain area (approximately 501 Lm square) in order to ensure mechanical precision during bonding and mechanical strength of bonding. There are disadvantages such as an increase in the area of the semiconductor chip or a limitation on the number of lead-out electrodes.

[発明の目的] この発明は上記のような事情を考慮してなされたもので
、その目的とするところは、大掛かりなポンディング装
置を必要とせず、簡単かつ容易にチップ型電子部品と配
線パターンとを接続することができ、かつ電気的信頼性
の高い電子部品の実装構造およびその実装方法を提供す
ることにある。
[Objective of the Invention] This invention was made in consideration of the above circumstances, and its purpose is to easily and easily connect chip-type electronic components and wiring patterns without requiring a large-scale bonding device. It is an object of the present invention to provide a mounting structure for electronic components that can be connected to the electronic components and has high electrical reliability, and a method for mounting the same.

[発明の要点] この発明は上記のような目的を達成するために、樹脂基
板中にチップ型の電子部品をその端子電極形成面を前記
樹脂基板の表面に近接させて埋め込んだ後、この電子部
品の端子電極部を被覆する前記樹脂基板の薄膜部にコン
タクトホールを形成し、前記樹脂基板の表面にコンタク
トホールを介して前記電子部品の端子電極に接続される
配線パターンを形成するようにしたものである。
[Summary of the Invention] In order to achieve the above object, the present invention embeds a chip-type electronic component in a resin substrate with its terminal electrode forming surface close to the surface of the resin substrate, and then embeds the electronic component in the resin substrate. A contact hole is formed in a thin film portion of the resin substrate that covers the terminal electrode portion of the component, and a wiring pattern is formed on the surface of the resin substrate to be connected to the terminal electrode of the electronic component via the contact hole. It is something.

[実施例1 以下、第1図および第2図を参照して、この発明の一実
施例を説明する。
[Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

第1図はチップ型電子部品の実装構造を示し。Figure 1 shows the mounting structure of a chip-type electronic component.

図中1は樹脂基板である。この樹脂基板lはポリエチレ
ン・テレフタレート(以下、PETと略称する)等の絶
縁性を有する熱可塑性樹脂等からなるシート状のもので
あり、その内部にはLS I?の半導体チップ2および
コンデンサチップ3が薄膜層4を残して埋め込まれてい
る。このtJ膜層4は樹脂基板lの一部であり、厚さが
51Lm以下、望ましくは2Bm程度で、半導体チップ
2の電極パッドおよびコンデンサチップ3の電極端子3
a、3aと対応する箇所にコンタクトホール4a・e・
がエツチング処理により形成されている。また、樹脂基
板1の上面には配線パターン5・Φ・が形成されている
。この配線パターン5―・・は樹脂基板1上に形成され
た導電性薄膜をエツチング処理することにより形成され
、その一部がコンタクトホール4a・・・を介して、そ
れぞれ半導体チップ2の電極パッドおよびコンデンサチ
ップ3の電極端子3a、3aに直接接続されている。
In the figure, 1 is a resin substrate. This resin substrate l is a sheet-like material made of an insulating thermoplastic resin such as polyethylene terephthalate (hereinafter abbreviated as PET), and inside it is an LSI? A semiconductor chip 2 and a capacitor chip 3 are embedded with a thin film layer 4 remaining. This tJ film layer 4 is a part of the resin substrate 1, has a thickness of 51 Lm or less, preferably about 2 Bm, and is used for the electrode pads of the semiconductor chip 2 and the electrode terminals of the capacitor chip 3.
Contact holes 4a, e, and 4a are provided at locations corresponding to a and 3a.
is formed by etching. Furthermore, a wiring pattern 5.Φ. is formed on the upper surface of the resin substrate 1. The wiring patterns 5-- are formed by etching a conductive thin film formed on the resin substrate 1, and a part of the wiring patterns 5-- are formed by etching the conductive thin film formed on the resin substrate 1, and a part thereof is connected to the electrode pads of the semiconductor chip 2 and the electrode pads of the semiconductor chip 2 through the contact holes 4a--. It is directly connected to the electrode terminals 3a, 3a of the capacitor chip 3.

次に、第2図を参照して、その製造方法について説明す
る。
Next, the manufacturing method will be explained with reference to FIG.

まず、第2図(a)に示すように、支持台6上に熱可塑
性フィルム7を配置する。この場合、支持台6は冷却a
JIIを持ち、8可塑性フイルム7を冷却するようにな
っている。熱可塑性フィルム7はPET等の絶縁性樹脂
からなり、加熱されると軟化するものであり、その上面
には半導体チップ2およびコンデンサチップ3が載置さ
れている。
First, as shown in FIG. 2(a), the thermoplastic film 7 is placed on the support base 6. In this case, the support stand 6 is
JII, and is designed to cool the plastic film 7. The thermoplastic film 7 is made of an insulating resin such as PET and softens when heated, and the semiconductor chip 2 and the capacitor chip 3 are placed on the top surface of the thermoplastic film 7.

この状態で、半導体チップ2およびコンデンサチップ3
を加熱しながら圧力を加えると、第2図(b)に示すよ
うに、各チップ2.3は熱可塑性フィルム7中に埋め込
まれる。この場合、支持台6は熱可塑性フィルム7の軟
化点よりもかなり低  ゛い場合例えば0℃に設定し、
チップ2.3の加熱温度は熱可塑性フィルム7の軟化点
よりかなり高くする。これは各チップ2.3に対する熱
可塑性フィルム7の熱接若性を良くするためである0例
えば軟化点が67℃であるPETに於ては加熱温度を1
50℃程度にする。そして、熱可塑性フィルム7の厚さ
が2pmの薄膜層4になるまで、各チップ2.3を加熱
圧入する。この場合、必ずしも2ILmの薄膜層4にな
るまで圧入する必要はなく、5pm以上であっても、埋
め込み後に1m素とフッ素のプラズマ中で全面均一なエ
ツチングを行なうことにより、最終的にFM膜層4を2
#Lm程度にしても良い。
In this state, semiconductor chip 2 and capacitor chip 3
When applying pressure while heating, each chip 2.3 is embedded in the thermoplastic film 7, as shown in FIG. 2(b). In this case, the support base 6 is set at a temperature considerably lower than the softening point of the thermoplastic film 7, for example, 0°C.
The heating temperature of the chip 2.3 is significantly higher than the softening point of the thermoplastic film 7. This is to improve the thermal adhesion of the thermoplastic film 7 to each chip 2.3. For example, for PET whose softening point is 67°C, the heating temperature is set to
The temperature should be around 50℃. Then, each chip 2.3 is heated and press-fitted until the thickness of the thermoplastic film 7 becomes the thin film layer 4 of 2 pm. In this case, it is not necessarily necessary to press-fit until the thin film layer 4 of 2 ILm is formed. Even if the thickness is 5 pm or more, the FM film layer can be etched uniformly over the entire surface in plasma of 1 m element and fluorine after implantation. 4 to 2
It may be about #Lm.

このように各チップ?、3を埋め込んだ後は、第2図(
C)に示すように、その裏面(上面)にエポキシ樹脂等
の絶縁材8を塗布し、平坦面にする。これにより、樹脂
基板1が形成されると共に、この樹脂基板l中に各チッ
プ2,3が埋め込まれる。この場合、各チップ2.3の
裏面側(上面側)は絶縁材8により塞がれて保護され、
表面側(下面側)は薄膜層4により保護される。
Each chip like this? , 3 after embedding Figure 2 (
As shown in C), an insulating material 8 such as epoxy resin is applied to the back surface (upper surface) to make it a flat surface. As a result, the resin substrate 1 is formed, and the chips 2 and 3 are embedded in this resin substrate l. In this case, the back side (top side) of each chip 2.3 is covered and protected by the insulating material 8,
The front side (lower side) is protected by a thin film layer 4.

この後、第2図(d)に示すように、樹脂基板lを上下
に反転させて薄膜層4側を上面側に向け、プラズマエツ
チングにより薄膜層4にコンタクトホール4a・・・を
形成する。即ち、樹脂基板lの上面にフォト・レジスト
膜を21.m程度の厚さに塗布し、フォト・リングラフ
ィ法により所定の位は(つまり、各チップ2,3の電極
パッドおよび電極端子3a、3aと対応する箇所)のフ
ォト・レジス)1111を除去した後、酸素とフッ素の
混合プラズマ中で薄膜層4をエツチングしてコンタクト
ホール4a・・・を形成する。この場合、プラズマ中で
は、フォト・レジスト膜も樹脂基板1の薄膜層4と同じ
ようにエツチングされるので、フォト・レジスト膜を剥
離する工程が不要となる。このようにしてコンタクトホ
ール4a・・會が形成されると、各チップ2.3の電極
パッドおよび電極端子3a、3aが外部に霧出する。
Thereafter, as shown in FIG. 2(d), the resin substrate 1 is turned upside down so that the thin film layer 4 side faces the upper surface side, and contact holes 4a are formed in the thin film layer 4 by plasma etching. That is, a photoresist film 21. The photoresist 1111 was applied to a thickness of about m, and the photoresist 1111 was removed at predetermined locations (that is, the locations corresponding to the electrode pads and electrode terminals 3a and 3a of each chip 2 and 3) using a photo phosphorography method. Thereafter, the thin film layer 4 is etched in a mixed plasma of oxygen and fluorine to form contact holes 4a. In this case, the photoresist film is also etched in the plasma in the same way as the thin film layer 4 of the resin substrate 1, so the step of peeling off the photoresist film is not necessary. When the contact holes 4a are formed in this way, the electrode pads and electrode terminals 3a, 3a of each chip 2.3 are sprayed out.

この後、第2図(e)に示すように、樹脂基板1の表面
(上面)に導電性薄膜9を形成する。この薄膜9はアル
ミ等の金属からなる薄い膜であり、直流スパッタ法によ
り樹脂基板1の表面に厚さ2ルm程度に蒸着される。し
かも、薄膜9の一部は薄膜層4のコンタクトホール4a
・・・を通り、各チップ2,3の電極パッドおよび電極
端子3a、3FLに直接接触して導通する。
Thereafter, as shown in FIG. 2(e), a conductive thin film 9 is formed on the surface (upper surface) of the resin substrate 1. This thin film 9 is a thin film made of metal such as aluminum, and is deposited to a thickness of about 2 m on the surface of the resin substrate 1 by DC sputtering. Moreover, a part of the thin film 9 is located in the contact hole 4a of the thin film layer 4.
. . , and directly contacts the electrode pads and electrode terminals 3a, 3FL of each chip 2, 3 for conduction.

この後、第2図(f)に示すように、上述したフォト・
リングラフィ法によって導電性部[9をエツチングして
所定の配線パターン5に形成する。このときには、各チ
ップ2.3の電極パッドおよび電極端子3a、3aを外
部へ導くパターンだけでなく、全ての配線パターンを樹
脂基板l上は形成する。このように配線パターン5が形
成された樹脂基板1上には、第2図(g)に示すように
、エポキシ樹脂等の保護膜10を塗布して、全体を保護
する。
After this, as shown in FIG. 2(f), the photo
The conductive portion [9 is etched by phosphorography to form a predetermined wiring pattern 5. At this time, not only the patterns for guiding the electrode pads and electrode terminals 3a, 3a of each chip 2.3 to the outside, but also all wiring patterns are formed on the resin substrate l. As shown in FIG. 2(g), a protective film 10 made of epoxy resin or the like is coated on the resin substrate 1 on which the wiring pattern 5 is formed in this manner to protect the entire surface.

従って、上記のような電子部品の実装構造および実装方
法によれば、大掛かりなポンディング装置を必要とせず
、簡単かつ容易にチップ型電子部品と配線パターンとを
接続することができると共に、かつ導通信頼性の高いも
のを得ることができる。この場合、特に薄膜層4側の樹
脂基板lの表面が均一な平面に形成され、しかもこの平
面上に形成された導電性S膜9をフォト−リソグラフィ
法によって配線パターン5を形成するようにしたので、
半導体チップ2の電極パッドが17zm角程度のもでも
充分に外部へ導くことができ、高密度の配線が可能とな
るばかりか、半導体チップ2の縮小、およびその電極の
高密度化等を図ることができる。
Therefore, according to the electronic component mounting structure and mounting method described above, it is possible to simply and easily connect a chip-type electronic component and a wiring pattern without the need for a large-scale bonding device, and also to ensure continuity. You can get something highly reliable. In this case, in particular, the surface of the resin substrate l on the side of the thin film layer 4 is formed into a uniform plane, and the wiring pattern 5 is formed on the conductive S film 9 formed on this plane by photolithography. So,
Even if the electrode pads of the semiconductor chip 2 are about 17 mm square, they can be sufficiently guided to the outside, making it possible not only to achieve high-density wiring, but also to reduce the size of the semiconductor chip 2 and increase the density of its electrodes. I can do it.

なお、この発明は上述した実施例に限定されることなく
1例えば、第3図に示すように各チップ2.3を埋め込
むようにしても良い、即ち、第3図(a)に示すように
、予め、熱可塑性フィルム7の下面にポリイミド等の耐
熱性樹脂よりなる薄膜層11を設ける。そして、熱可塑
性フィルム7の上面に各チップ2,3をa置する。この
後、上述した実施例と同様に、各チップ2,3を加熱し
なから熱可塑性フィルム7中に圧入する。この場合には
、支持台6も加熱手段として併用できる。
Note that the present invention is not limited to the above-described embodiment, and for example, each chip 2.3 may be embedded as shown in FIG. 3 (a). , a thin film layer 11 made of a heat-resistant resin such as polyimide is provided on the lower surface of the thermoplastic film 7 in advance. Then, each of the chips 2 and 3 is placed a on the upper surface of the thermoplastic film 7. Thereafter, each of the chips 2 and 3 is press-fitted into the thermoplastic film 7 without being heated, as in the embodiment described above. In this case, the support stand 6 can also be used as a heating means.

モして熱可塑性フィルム7が残らないように、各チップ
2,3を圧入して、その各下面を薄膜N11に密着させ
る0次に、第3図(C)に示すように、熱可塑性フィル
ム7の上面にエポキシ樹脂等の絶縁材8を塗布して各チ
ップ2.3の裏面側(上面側)を塞いで保護する。この
後は、上述した実施例と全く同様に、コンタクトホール
および配線パターンを形成すれば良い、このようにすれ
ば、上述した実施例のように各チップ2.3の埋め込み
量を調整する必要がないので、より簡単かつ良好に各チ
ップ2.3を埋め込むことができる。また、第3図で説
明した実施例のように樹脂基板を二層のフィルムで構成
する場合には、予め、ベースフィルム(第3図の熱可塑
性フィルム7に相当)に各チップ2.3が嵌合する孔を
形成し、その下面にポリイミド等からなる薄いフィルム
(第3図の薄膜層11に相当)を設けて、上記孔内にそ
れぞれ各チップ2.3を配置するようにしても良い、こ
のようにすれば、より一層埋め込み作業を容易に行なう
ことができる。
Press-fit each chip 2, 3 so that the thermoplastic film 7 does not remain, and bring the bottom surface of each chip into close contact with the thin film N11.Next, as shown in FIG. 3(C), the thermoplastic film An insulating material 8 such as epoxy resin is applied to the upper surface of each chip 2.3 to cover and protect the back surface side (upper surface side) of each chip 2.3. After this, contact holes and wiring patterns can be formed in exactly the same manner as in the above-mentioned embodiment. By doing this, it is not necessary to adjust the amount of embedding of each chip 2.3 as in the above-mentioned embodiment. Therefore, each chip 2.3 can be embedded more easily and better. In addition, when the resin substrate is composed of a two-layer film as in the embodiment explained in FIG. 3, each chip 2.3 is placed on the base film (corresponding to the thermoplastic film 7 in FIG. A fitting hole may be formed, a thin film made of polyimide or the like (corresponding to the thin film layer 11 in FIG. 3) may be provided on the underside of the hole, and each chip 2.3 may be placed in each hole. In this way, the embedding work can be performed even more easily.

また、第2図及び第3図に示した実施例に於て埋め込む
電子部品が半導体チップである場合、第4図に示すよう
に半導体チップの圧入終了後、半導体チップの裏面をエ
ツチングするようにしても良い、即ち、第4図(a)(
第2図(b)及び第3図(b)の対応図)に示すように
、熱可塑性フィルム7に半導体チップ2を圧入した後、
弗酸、硝酸、硫酸の混合液によるウェットエツチング、
或いは弗素プラズマによるドライエツチング等任意のエ
ツチング手法で半導体チップ2の裏面をエツチングし、
第4図(b)に示すように半導体チップ2の厚みを15
0μm程度にする。しかる後に、第4図(C)に示すよ
うに、半、導体チップ2のエツチングにより生じた熱可
塑性フィルム7の凹部に熱可塑性樹脂、望ましくは熱可
塑性フィルム7と同一の樹脂をポツティングして封止し
、更に熱可塑性フィルム7の裏面を研唐するか或いはリ
フローして第4図(d)に示すように平坦化させる。こ
の方法によれば、ウェハのスクライブ段階で厚みが30
0gm以上あった半導体チップを150gm或いはそれ
以下にまで薄くすることができる。
Furthermore, in the embodiments shown in FIGS. 2 and 3, if the electronic component to be embedded is a semiconductor chip, the back surface of the semiconductor chip is etched after the semiconductor chip is press-fitted, as shown in FIG. 4(a) (
As shown in FIGS. 2(b) and 3(b), after press-fitting the semiconductor chip 2 into the thermoplastic film 7,
Wet etching with a mixture of hydrofluoric acid, nitric acid, and sulfuric acid,
Alternatively, the back surface of the semiconductor chip 2 is etched by any etching method such as dry etching using fluorine plasma,
As shown in FIG. 4(b), the thickness of the semiconductor chip 2 is 15 mm.
The thickness should be approximately 0 μm. Thereafter, as shown in FIG. 4(C), a thermoplastic resin, preferably the same resin as the thermoplastic film 7, is potted into the recesses of the thermoplastic film 7 created by etching the semiconductor chip 2, and sealed. Then, the back surface of the thermoplastic film 7 is polished or reflowed to make it flat as shown in FIG. 4(d). According to this method, the thickness of the wafer is 30 mm at the scribing stage.
A semiconductor chip having a thickness of 0 gm or more can be made thinner to 150 gm or less.

[発明の効果] 以上説明したように、この発明は、樹脂基板中にチップ
型の電子部品をその端子電極形成面を前記樹脂基板の表
面に近接させて埋め込んだ後、この電子部品の端子電極
部を被覆する前記樹脂基板の薄膜部にコンタクトホール
を形成し、前記樹脂基板の表面にコンタクトホールを介
して前記電子部品の端子電極に接続される配線パターン
を形成するようにしたので、大掛かりなポンディング装
置を必要とせず、簡単かつ容易にチップ型電子部品と配
線パターンとを接続することができ、かつ電気的信頼性
の高いものを得ることができる。
[Effects of the Invention] As explained above, in the present invention, after a chip-type electronic component is embedded in a resin substrate with its terminal electrode forming surface being brought close to the surface of the resin substrate, the terminal electrode of this electronic component is embedded. A contact hole is formed in the thin film part of the resin substrate that covers the electronic component, and a wiring pattern is formed on the surface of the resin substrate to be connected to the terminal electrode of the electronic component through the contact hole. A chip-type electronic component and a wiring pattern can be connected simply and easily without the need for a bonding device, and a product with high electrical reliability can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図はこの発明の一実施例を示し、第1
図は電子部品の実装構造を示す要部拡大断面図、第2図
(a)〜(g)はその実装方法を示す工程図、第3図(
a)〜(c)は変形例の要部工程図、第4図(a)〜(
c)は異なる変形例の要部工程図である。 l・・・・・・樹脂基板、2・・・用半導体チップ、3
・旧・・コンデンサチップ、3a・・・・・・電極端子
、4.11・・・・・・l8Ji膜層、5・・・・・・
配線パターン、7・旧・・熱可塑性フィルム、8・・・
・・・絶縁材、9・・・・・・導電性薄膜。 第4図 史形4タク/1零舒X手!図 第2図 欠装於粕〒、TT−程口 手続補正書(方式) 昭和61年4月24日 昭和60年特許願第298982号 2、発明の名称 電子部品の実装構造およびその実装方法3、補正をする
者 事件との関係  特許出願人 住所 東京都新宿区西新宿2丁目6番1号名称 (14
4)カシオ計算機株式会社代表者  樫  尾  忠 
 雄 4、代理人 住所 東京都港区西新橘l−T目13番4号T−Sビル
3階〜\ 氏名 弁理士(7734)町 1)俊 蓋二;−5、補
正命令の日付 昭和61年3月250(発送口) 6、補正の対象 (1)明細書の「図面の簡単な説明」の欄。 7、補正の内容 (1)明細書の第13頁第11行に「第4図(a)〜(
C)」とあるのを「第4図(a)〜(d)」と訂正する
FIG. 1 and FIG. 2 show one embodiment of the present invention.
The figure is an enlarged sectional view of the main part showing the mounting structure of electronic components, Figures 2 (a) to (g) are process diagrams showing the mounting method, and Figure 3 (
a) to (c) are main part process diagrams of the modified example, and Fig. 4 (a) to (
c) is a main part process diagram of a different modification. l...resin substrate, 2... semiconductor chip, 3
・Old...Capacitor chip, 3a...Electrode terminal, 4.11...l8Ji film layer, 5...
Wiring pattern, 7. Old... Thermoplastic film, 8...
... Insulating material, 9... Conductive thin film. Figure 4: Historical form 4 taku/1 zero shu x hand! Figure 2 Missing page, TT-Procedure amendment (method) April 24, 1985 Patent application No. 298982, filed in 1985 2 Title of invention Electronic component mounting structure and its mounting method 3 , Relationship with the person making the amendment Patent applicant address 2-6-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo Name (14
4) Tadashi Kashio, Representative of Casio Computer Co., Ltd.
Yu 4, Agent Address: 3rd Floor, T-S Building, 13-4, Nishishintachibana 1-T, Minato-ku, Tokyo ~\ Name: Patent Attorney (7734) Town 1) Shun Kaji; -5, Date of Amendment Order: 1988 March 250 (shipping port) 6. Subject of amendment (1) "Brief explanation of drawings" column of the specification. 7. Contents of amendment (1) In page 13, line 11 of the specification, “Figure 4 (a) to (
C)" should be corrected to "Fig. 4 (a) to (d)."

Claims (2)

【特許請求の範囲】[Claims] (1)チップ型の電子部品を配線基板に実装する電子部
品の実装構造に於て、前記配線基板は樹脂基板とこの樹
脂基板の表面に形成された配線パターンとからなり、前
記電子部品は前記樹脂基板中にその端子電極形成面を配
線パターン形成面に近接させて埋め込まれ、且つその端
子電極はこの電極上の樹脂基板の薄膜部に形成されたコ
ンタクトホールを介して前記配線パターンに直接接続さ
れていることを特徴とする電子部品の実装構造。
(1) In an electronic component mounting structure in which a chip-type electronic component is mounted on a wiring board, the wiring board is composed of a resin substrate and a wiring pattern formed on the surface of the resin substrate, and the electronic component is The terminal electrode is embedded in a resin substrate with its terminal electrode forming surface close to the wiring pattern forming surface, and the terminal electrode is directly connected to the wiring pattern through a contact hole formed in a thin film portion of the resin substrate above the electrode. An electronic component mounting structure characterized by:
(2)チップ型の電子部品を配線基板に実装する電子部
品の実装方法に於て、前記配線基板のベースとなる樹脂
基板中に前記電子部品をその端子電極形成面を前記樹脂
基板の表面に近接させて埋め込む工程と、この電子部品
の端子電極部を被覆する前記樹脂基板の薄膜部にコンタ
クトホールを形成する工程と、前記樹脂基板の表面にコ
ンタクトホールを介して前記電子部品の端子に接続され
る配線パターンを形成する工程とからなる電子部品の実
装方法。
(2) In an electronic component mounting method in which a chip-type electronic component is mounted on a wiring board, the electronic component is placed in a resin substrate that serves as the base of the wiring board, and the terminal electrode forming surface thereof is placed on the surface of the resin substrate. a step of embedding the electronic component in close proximity; a step of forming a contact hole in a thin film portion of the resin substrate that covers the terminal electrode portion of the electronic component; and a step of connecting to the terminal of the electronic component through the contact hole on the surface of the resin substrate. A method for mounting an electronic component, comprising the step of forming a wiring pattern.
JP60298982A 1985-12-31 1985-12-31 Mounting structure of electronic parts and their mounting method Pending JPS62158336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60298982A JPS62158336A (en) 1985-12-31 1985-12-31 Mounting structure of electronic parts and their mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60298982A JPS62158336A (en) 1985-12-31 1985-12-31 Mounting structure of electronic parts and their mounting method

Publications (1)

Publication Number Publication Date
JPS62158336A true JPS62158336A (en) 1987-07-14

Family

ID=17866700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60298982A Pending JPS62158336A (en) 1985-12-31 1985-12-31 Mounting structure of electronic parts and their mounting method

Country Status (1)

Country Link
JP (1) JPS62158336A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198385A (en) * 1991-01-11 1993-03-30 Harris Corporation Photolithographic formation of die-to-package airbridge in a semiconductor device
US5877550A (en) * 1996-07-31 1999-03-02 Taiyo Yuden Co., Ltd. Hybrid module and method of manufacturing the same
JP2013514637A (en) * 2009-12-18 2013-04-25 シュバイツァー エレクトロニク アーゲー Conductive structural element and method for manufacturing the conductive structural element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5198385A (en) * 1991-01-11 1993-03-30 Harris Corporation Photolithographic formation of die-to-package airbridge in a semiconductor device
US5877550A (en) * 1996-07-31 1999-03-02 Taiyo Yuden Co., Ltd. Hybrid module and method of manufacturing the same
JP2013514637A (en) * 2009-12-18 2013-04-25 シュバイツァー エレクトロニク アーゲー Conductive structural element and method for manufacturing the conductive structural element
US9456500B2 (en) 2009-12-18 2016-09-27 Schweizer Electronic Ag Conductor structure element and method for producing a conductor structure element

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