JPS62156845A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS62156845A
JPS62156845A JP60297016A JP29701685A JPS62156845A JP S62156845 A JPS62156845 A JP S62156845A JP 60297016 A JP60297016 A JP 60297016A JP 29701685 A JP29701685 A JP 29701685A JP S62156845 A JPS62156845 A JP S62156845A
Authority
JP
Japan
Prior art keywords
metal layer
bed part
semiconductor chip
lead frame
bed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60297016A
Other languages
Japanese (ja)
Inventor
Masahide Kudo
工藤　眞秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60297016A priority Critical patent/JPS62156845A/en
Publication of JPS62156845A publication Critical patent/JPS62156845A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To form a semiconductor device in a short time and also, to obtain a lead frame to be formed at a low cost by a method wherein the bed part to be mounted with a semiconductor chip and the outer leads to be continuously connected to the inner leads are each coated with metal layers whose fusing temperatures are mutually different. CONSTITUTION:A bed part 1 and outer leads 3 are each coated with metal layers whose fusing temperatures are mutually different and the metal layers each can be made a fusing temperature difference hold. The metal layer of the bed part 1 is one to act as a mounting agent for a semiconductor chip 5 and when the metal layer is heated at its fusing temperature after the semiconductor chip 5 is placed on the bed apart 1, the metal layer of the bed part 1 is fused between the semiconductor chip 5 and the bed part 1 and when the metal layer is cooled, the semiconductor chip and the bed part are firmly bonded. It is desirable to use a material of a fusing temperature lower than that of the metal layer of the outer leads 3 for the metal layer of the bed part 1. Thereby, a silver paste to be used as a mounting agent becomes unnecessary for the bed part 1, a semiconductor device can be formed in a short time, and at the same time, the cost of a lead frame becomes a low cost.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体チップがモールド樹脂によって１１止さ
れる半導体装；どのリードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device; any lead frame in which a semiconductor chip is fixed with a molding resin.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

第６図に樹脂封止型半導体装置の斜視図を示す。 FIG. 6 shows a perspective view of a resin-sealed semiconductor device.

タイバー２１に両側から支持されたベッド部２２と、ベ
ッド部２２の周囲に一定間隔で配設された複数のインナ
ーリード２３と、インナーリード２３の外側に連設され
たアウターリード２４とによってリードフレームが構成
されている。A lead frame is constructed by a bed section 22 supported by tie bars 21 from both sides, a plurality of inner leads 23 arranged at regular intervals around the bed section 22, and an outer lead 24 connected to the outside of the inner leads 23. is configured.

リードフレームのベッド部２２上には半導体デツプ２５
がマウントされ、半導体チップ２５の電極とインナーリ
ード２３とが金線、アルミニウム線等からなるボンディ
ングワイヤ２６によって接続され、二点鎖線で示す部分
がモールド樹脂によって封止されて半導体装置が！ｇ造
されるようになっている。かかる半導体装置において、
リードフレームのベッド部２２には従来、銀メッキが施
されるか、メッキが施されておらず、ベッド部２２には
マウント剤としての銀ペーストがボンディングされ、こ
の銀ペーストの硬化によって半導体チップ２５の固着が
行なわれていた。又、モールド樹脂の外部に延びるアウ
ターリード２／ｌは樹脂封止の後に、錫メッキ、ハンダ
メッキあるいはハンダ付は等によって表面保護膜が形成
されていた。A semiconductor depth 25 is placed on the bed portion 22 of the lead frame.
is mounted, the electrodes of the semiconductor chip 25 and the inner leads 23 are connected by bonding wires 26 made of gold wire, aluminum wire, etc., and the portion shown by the two-dot chain line is sealed with molding resin to complete the semiconductor device! It is now being built. In such a semiconductor device,
Conventionally, the bed portion 22 of the lead frame is plated with silver or not plated, and a silver paste as a mounting agent is bonded to the bed portion 22, and the semiconductor chip 25 is bonded to the bed portion 22 as a mounting agent. fixation was taking place. Further, after the outer leads 2/l extending outside the mold resin are sealed with resin, a surface protective film is formed by tin plating, solder plating, soldering, or the like.

従って、従来の半導体装置は半導体チップ２６のマウン
ト剤である銀ベース１〜の硬化に長時間を要すると共に
、銀ペーストの使用により高価となっていた。又、アウ
ターリード２４も樹脂封止後に表面保護膜を形成するた
め、製造工程数が多くなるという問題があった。Therefore, in the conventional semiconductor device, it takes a long time to cure the silver base 1 which is the mounting agent for the semiconductor chip 26, and the cost is increased due to the use of silver paste. Furthermore, since a surface protective film is formed on the outer lead 24 after resin sealing, there is a problem in that the number of manufacturing steps increases.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、半導体装置を短時間に製造でき、しか
も安価に提供するためのリードフレームを提供すること
にある。An object of the present invention is to provide a lead frame that allows semiconductor devices to be manufactured in a short time and at low cost.

〔発明の概要〕[Summary of the invention]

本発明によるリードフレームは、ベッド部とアウターリ
ードとを溶融温度の異なる金属層ひ被覆したものである
。そしてベッド部上に形成された金属層はその溶融温度
まで加熱されることぐ溶融し、ベッド部上に載置された
半導体チップのマウン１−剤として作用するから、銀ペ
ーストが不要となり、その硬化時間も不要となる。又、
アウターリード上に形成された金属層は表面像″ｆ！膜
となるから樹脂封止後の保護膜形成工程を省略すること
ができる。The lead frame according to the present invention has a bed portion and an outer lead coated with metal layers having different melting temperatures. The metal layer formed on the bed part melts as it is heated to its melting temperature, and acts as a mounting agent for the semiconductor chip placed on the bed part, eliminating the need for silver paste. There is no need for curing time. or,
Since the metal layer formed on the outer lead becomes a surface image "f! film", the step of forming a protective film after resin sealing can be omitted.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明を図示する実施例により、さらに詳述する
。Hereinafter, the present invention will be further explained in detail with reference to illustrative examples.

第１図は本発明の一実施例によるリードフレームの斜視
図である。ベッド部１とインナーリード２とアウターリ
ード３とによってリードフレームが構成されている。ベ
ッド部１はタイバー４にＪ：つて両側から支持されてお
り、上面に半導体デツプ５がマウン１−されるようにな
っている。インナーリード２はベッド部１の周囲に一定
の間隔を有して配設され、アウターリード３はインナー
リード２の外側に連設されている。インナーリード２の
内端部は銀メッキが施されてボンディング部２ａとなっ
ている。すなわち、各インナーリード２のボンディング
部２ａには半導体チップ５の電極に一端が接続されたボ
ンディングワイヤ（図示せず）の（（！！端が当接され
て超音波振動等によって、ボンディングワイヤの他端が
接続されるものである。第２図はこのような半導体装置
に使用されるリードフレームの平面図である。フレーム
枠６の長手方向にリードフレームが複数形成されており
、各リードフレームの中央部に位置するベッド部１はフ
レーム枠６から内方に延びるタイバー４に支持されてい
る。FIG. 1 is a perspective view of a lead frame according to an embodiment of the present invention. The bed portion 1, inner leads 2, and outer leads 3 constitute a lead frame. The bed portion 1 is supported from both sides by tie bars 4, and a semiconductor depth 5 is mounted on the top surface. The inner leads 2 are arranged around the bed portion 1 at regular intervals, and the outer leads 3 are connected to the outside of the inner leads 2. The inner end portion of the inner lead 2 is plated with silver to form a bonding portion 2a. That is, the bonding portion 2a of each inner lead 2 is abutted with a bonding wire (not shown) whose one end is connected to an electrode of the semiconductor chip 5, and the bonding wire is heated by ultrasonic vibration or the like. The other end is connected. Fig. 2 is a plan view of a lead frame used in such a semiconductor device. A plurality of lead frames are formed in the longitudinal direction of the frame frame 6, and each lead frame A bed portion 1 located at the center of the frame 6 is supported by tie bars 4 extending inward from a frame 6.

このようなリードフレームにおいて、ベッド部１および
アウターリード３は異なる溶融１ｉＩａ度の金属層によ
って被覆されている。これらの金属層は、例えば錫と鉛
の組成比を異ならせることで溶融温度斧を持たけること
ができ、錫と鉛の組成比を３ニアとしたハンダをベッド
部１にメッキし、錫と鉛の組成比を１＝９としたハンダ
をアウターリード３にメツキリ゛ることで実現される。In such a lead frame, the bed portion 1 and the outer lead 3 are coated with metal layers of different melting degrees. These metal layers can have melting temperature axes by, for example, varying the composition ratio of tin and lead, and the bed portion 1 is plated with solder with a composition ratio of tin and lead of 3 nia. This is achieved by applying solder with a lead composition ratio of 1=9 to the outer lead 3.

ここで、ベッド部１の金属層は半導体チップ５のマｔク
ン１〜剤として作用する乙のである。すなわら、半導体
チップ５をベッド部１に載置後に、その？８融温度まで
ベッド部１又はリードフレーム全体を加熱すると、ベッ
ド部１の金属層は半導体デツプ５とベッド部１との間で
溶け、冷ＩＪＩするとこれらを強固に結合する。この場
合、ベッド部１の金属層はアウターリード３の金属層よ
りも溶融温度の低い素材を使用するのが好ましい。ベッ
ド部の金属層の溶融時点ではアウターリード３の金属層
は溶けることなくアウターリード３の被覆状態を維持す
るからである。従って、ベッド部１にはマウント剤とし
ての銀ペーストは不要となるから、その硬化時間も不要
となり半導体装置を短時間で製造できると共に、安価と
なる。一方、アウターリード３の金属層は表面像″、Ｉ
！Ｌｌ１２として寄与し、樹脂封止後にアウターリード
３にメッキ等を施して表面保護膜を形成する工程が不要
となる。Here, the metal layer of the bed portion 1 acts as a matrix for the semiconductor chip 5. That is, after the semiconductor chip 5 is placed on the bed portion 1, the ? When the bed section 1 or the entire lead frame is heated to a melting temperature of 8, the metal layer of the bed section 1 melts between the semiconductor depth 5 and the bed section 1, and cold IJI firmly bonds them together. In this case, the metal layer of the bed portion 1 is preferably made of a material having a lower melting temperature than the metal layer of the outer lead 3. This is because, at the time when the metal layer of the bed portion melts, the metal layer of the outer lead 3 does not melt and maintains the covering state of the outer lead 3. Therefore, since silver paste as a mounting agent is not required in the bed portion 1, the curing time is also unnecessary, and the semiconductor device can be manufactured in a short time and at low cost. On the other hand, the metal layer of the outer lead 3 has a surface image "I",
! It contributes as L112, and the process of forming a surface protection film by plating or the like on the outer lead 3 after resin sealing becomes unnecessary.

次に以上のようなリードフレームの製造を第３図ないし
第５図により説明する。第３図は￥Ｊ造工稈の流れを示
してａ５す、左側からアルカリ液が貯留された脱脂槽１
０、水が貯留された洗浄槽１１、第１の金属が溶融され
た第１処理槽１２、水が貯留された洗浄槽１３、第２の
金属が溶融された第２処理槽１４、水が貯留された洗浄
槽１５が順に配設されている。そして、リードフレーム
を搬送するコンベアが一連の槽１０〜１５に連続的に浸
漬されている。リードフレームは第２図に示すようにフ
レーム枠６に複数連設された状態で、第３図の左側から
供給され、脱脂槽１０内で脱脂処理が行なわれ、洗浄槽
１１で付着しているアルカリ液が除去される。次に、第
１処理（ａ１２内で第１の金属層がメッキされる。この
第１処理槽１２ではアウターリード３に表面保護膜とな
る第１の金属層が被覆されるようになっＣおり、ベッド
部１おにびインナーリード２はマスクによって上下面が
覆われ、第１の金属層の付着が防止されている。Next, manufacturing of the lead frame as described above will be explained with reference to FIGS. 3 to 5. Figure 3 shows the flow of the ￥J artificial culm.
0, a cleaning tank 11 in which water is stored, a first treatment tank 12 in which a first metal is melted, a cleaning tank 13 in which water is stored, a second treatment tank 14 in which a second metal is melted; The stored cleaning tanks 15 are arranged in order. A conveyor for transporting lead frames is continuously immersed in a series of tanks 10-15. As shown in FIG. 2, a plurality of lead frames are connected to the frame frame 6 and are supplied from the left side in FIG. The lye is removed. Next, a first process (a first metal layer is plated in a12). The upper and lower surfaces of the bed portion 1 and inner leads 2 are covered with masks to prevent the first metal layer from adhering.

第４図は第１処理槽１２を通過したリードフレームの平
面図であり、マスクされたベッド部１、インナーリード
２を除く他の部分に第１の金属層が被覆されている。次
にリードフレームは洗浄された後、′！５２処理檜１４
に移送される。この第２処理槽１４ではベッド部１を第
２の金属層て被覆するものである。このため、ベッド部
１以外のインナーリード２　ｄ３よびアウターリード３
を含む部分がマスクによって覆われて第２処理槽１４に
供給される。第５図は第２処理槽１４を通過したり一ド
フレームの平面図であり、ベッド部１に第２の金属層が
被覆されている。FIG. 4 is a plan view of the lead frame that has passed through the first processing tank 12, and the other parts except the masked bed part 1 and inner leads 2 are coated with the first metal layer. Next, the lead frame is cleaned and then ′! 52 treated cypress 14
will be transferred to. In this second treatment tank 14, the bed portion 1 is coated with a second metal layer. Therefore, the inner lead 2 d3 and the outer lead 3 other than the bed part 1
The portion containing the liquid is covered with a mask and supplied to the second processing tank 14. FIG. 5 is a plan view of the frame passing through the second treatment tank 14, in which the bed portion 1 is coated with a second metal layer.

なお、上記実施例ではハンダを用いたが金属層として、
ハンダ以外の他の金属を使用してもよい。In addition, although solder was used in the above embodiment, as a metal layer,
Other metals than solder may also be used.

〔発明の効果〕〔Effect of the invention〕

以上のとおり本発明によれば、ベッド部とアウターリー
ドとを溶融温度の異なる金属層で被覆し、ベッド部の金
属層を半導体チップのマウント剤として適用し、アウタ
ーリードの金属層を表面保護膜どして適用したから、マ
ウント剤である銀ペースト・が不要となり半導体装置を
短時間で安価に製造できると共に、樹脂１１止後のアウ
ターリードのメッキ処理も不要となり製造工程数を削減
することができる。As described above, according to the present invention, the bed portion and the outer leads are coated with metal layers having different melting temperatures, the metal layer of the bed portion is applied as a mounting agent for the semiconductor chip, and the metal layer of the outer leads is coated with a surface protective film. By applying this method, silver paste, which is a mounting agent, is no longer required, making it possible to manufacture semiconductor devices in a short period of time and at low cost.In addition, plating of the outer leads after resin 11 is attached is no longer necessary, reducing the number of manufacturing steps. can.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例によるリードフレーム斜視図
、第２図は同リードフレームの平面図、第３図は同リー
ドフレームを！Ｉｌ造する製造装置の正面図、第４図Ｊ
３よび第５図は製造途中にａ５けるリードフレームの平
面図、第６図は従来のリードフレームの斜視図である。 １・・・ベッド部、３・・・アウターリード。 出願人代理人　　１１ｉ　　　藤　　−雄烙ユ図 箸４図 箸５図Fig. 1 is a perspective view of a lead frame according to an embodiment of the present invention, Fig. 2 is a plan view of the lead frame, and Fig. 3 is a diagram of the same lead frame! Front view of manufacturing equipment, Figure 4J
3 and 5 are plan views of the lead frame at A5 during manufacture, and FIG. 6 is a perspective view of the conventional lead frame. 1...Bed part, 3...Outer lead. Applicant's representative 11i Wisteria - Xionghuanyu diagram chopsticks 4 diagram chopsticks 5 diagram

Claims (1)

【特許請求の範囲】 １、半導体チップがマウントされるベッド部と、インナ
ーリードに連設されるアウターリードとをそれぞれ溶融
温度の異なる金属層で被覆したことを特徴とするリード
フレーム。 ２、特許請求の範囲第１項記載のリードフレームにおい
て、前記金属層が錫と鉛の組成比が異なるハンダである
ことを特徴とするリードフレーム。[Claims] 1. A lead frame characterized in that a bed portion on which a semiconductor chip is mounted and an outer lead connected to an inner lead are respectively coated with metal layers having different melting temperatures. 2. The lead frame according to claim 1, wherein the metal layer is a solder having a different composition ratio of tin and lead.
JP60297016A 1985-12-28 1985-12-28 Lead frame Pending JPS62156845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60297016A JPS62156845A (en) 1985-12-28 1985-12-28 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60297016A JPS62156845A (en) 1985-12-28 1985-12-28 Lead frame

Publications (1)

Publication Number Publication Date
JPS62156845A true JPS62156845A (en) 1987-07-11

Family

ID=17841149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60297016A Pending JPS62156845A (en) 1985-12-28 1985-12-28 Lead frame

Country Status (1)

Country Link
JP (1) JPS62156845A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647547A (en) * 1987-06-29 1989-01-11 Nec Corp Resin-sealed semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647547A (en) * 1987-06-29 1989-01-11 Nec Corp Resin-sealed semiconductor device

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