JPS647547A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPS647547A
JPS647547A JP16374487A JP16374487A JPS647547A JP S647547 A JPS647547 A JP S647547A JP 16374487 A JP16374487 A JP 16374487A JP 16374487 A JP16374487 A JP 16374487A JP S647547 A JPS647547 A JP S647547A
Authority
JP
Japan
Prior art keywords
tin
lead
lead alloy
semiconductor device
alloy coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16374487A
Other languages
Japanese (ja)
Inventor
Tomoichi Oku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16374487A priority Critical patent/JPS647547A/en
Publication of JPS647547A publication Critical patent/JPS647547A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To lower the cost and shorten the manufacturing time by a method wherein a semiconductor device is provided with a mount to carry a semiconductor element through the intermediary of a tin-lead alloy coating and with an outer lead that is also a tin-lead alloy coating with its melting temperature point higher than that used for the mount. CONSTITUTION:A resin-sealed semiconductor device of this design includes a semiconductor element 4, a mount 2 to carry the semiconductor element 4 through the intermediary of a coating of a tin-lead alloy, and outer leads 1 constituting a higher-melting tin-lead alloy coating together with regions other than wire-bonding regions. Such a combination of coatings may be obtained by using a lead frame with its components plated prior to assembly. The difference in melting temperature between the two tin-lead alloys contributes to the elimination of difficulties in the assembling process. The design dispenses with a step for providing the outer leads 1 with a tin or tin-lead alloy coating, after encapsulation in a sealing resin 7.
JP16374487A 1987-06-29 1987-06-29 Resin-sealed semiconductor device Pending JPS647547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16374487A JPS647547A (en) 1987-06-29 1987-06-29 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16374487A JPS647547A (en) 1987-06-29 1987-06-29 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS647547A true JPS647547A (en) 1989-01-11

Family

ID=15779856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16374487A Pending JPS647547A (en) 1987-06-29 1987-06-29 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS647547A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04134851A (en) * 1990-09-27 1992-05-08 Nec Corp Lead frame
KR19990016048A (en) * 1997-08-12 1999-03-05 윤종용 Solder plated lead frame and manufacturing method of semiconductor chip package using the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62156845A (en) * 1985-12-28 1987-07-11 Toshiba Corp Lead frame

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62156845A (en) * 1985-12-28 1987-07-11 Toshiba Corp Lead frame

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04134851A (en) * 1990-09-27 1992-05-08 Nec Corp Lead frame
KR19990016048A (en) * 1997-08-12 1999-03-05 윤종용 Solder plated lead frame and manufacturing method of semiconductor chip package using the same

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