KR19990016048A - Solder plated lead frame and manufacturing method of semiconductor chip package using the same - Google Patents

Abstract

The present invention relates to a pre-plated frame (PPF) in which a solder is previously plated on the lead frame. In order to eliminate the de-flashing process and the plating process in the manufacturing process of the semiconductor chip package using the lead frame, a lead frame in which palladium and nickel are previously plated was used in the lead frame manufacturing step. However, this palladium / nickel pre-plated lead is used. The frame is applicable only to the copper lead frame and has a problem of cracking or inferior solder bonding because of its high strength. In order to solve this problem, the present invention provides a solder pre-plated lead frame in which a solder plating layer is formed only on an external lead portion by using a mask in manufacturing the lead frame. The solder pre-plated lead frame according to the present invention can shorten the package manufacturing process, reduce manufacturing costs, and can be applied to iron / nickel lead frames. In particular, the solder bonding is excellent, there is an advantage that can be in-line package manufacturing process.

Description

Solder plated lead frame and manufacturing method of semiconductor chip package using same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used in the manufacture of a semiconductor chip package, and more particularly, to a lead frame in which solder is partially plated before being put into a manufacturing process of a semiconductor chip package and a semiconductor chip package using the same. It is about a method.

Today, the electronics industry is becoming lighter, smaller, faster, more versatile, and higher in performance, and is moving toward the trend of manufacturing low-cost products with high reliability. One of the key technologies that help achieve these product design goals is package assembly. The main functions of the package manufacturing are 1) to provide a current path for supplying power to the circuit of the semiconductor chip, 2) to distribute electrical signals to and from the semiconductor chip, 3) to remove heat generated from the circuit of the semiconductor chip, And 4) supporting semiconductor chips and protecting them from external contamination.

The semiconductor chip package is not only mechanically bonded to an external main board through a lead frame, but also makes an electrical connection between the semiconductor chip inside the package and the external main board through the lead frame. 2 illustrates a structure of a semiconductor chip package 20 of a small outline package (SOP), which is an example of a semiconductor chip package. 1 illustrates a structure of a lead frame 10 used to manufacture a package 20 of the SOPs shown in FIG. 2. The package of FIG. 2 is shown based on a cross section taken along line II-II of FIG. 1.

1 and 2, the semiconductor chip 21 having the plurality of input / output pads 21a formed thereon is adhered to the chip pad 11 of the lead frame 10 by an adhesive 22. The input / output pad 21a is electrically connected to the inner lead 12 of the lead frame 10 by a gold wire 23 (Au wire). The package body 24 is formed of an epoxy resin, and the semiconductor chip 21, the gold wire 23, the chip pad 11, and the inner lead 12 are enclosed in the package body 24. The outer lead 13 of the lead frame 10 protruding out of the package body 24 is plated with solder 25, bent into a predetermined shape and bonded to a main substrate (not shown). The lead frame 10 is mainly made of copper (Cu) or iron / nickel alloy (Fe / Ni alloy or alloy 42). 14 indicates a dam bar, which prevents the flow of epoxy resin to form a package body 24, and is removed in the state of the completed package 20 as shown in FIG. 2. 1, 15 is an outer portion of the lead frame 10 for the transport of the package semifinished product during the manufacture of the package 20, which is also removed in the state of the completed package 20.

The semiconductor chip 21 is provided from a wafer (not shown), which is a wafer fabrication process for forming a plurality of chips (ie, integrated circuits) on a silicon disc and each chip constituting the wafer. EDS (electrical die sorting) process that checks the electrical properties of the finished and entered into the package manufacturing process. The package 20 shown in FIG. 2 is manufactured through each of the following manufacturing processes, as shown in FIG. Reference numerals cited below are those shown in FIGS. 1 to 3.

Tape is attached to the back side of the wafer which is put into the package manufacturing process by using a ring-wafer mounting process (wafer mount) (31), and the wafer is cut by cutting blades along the cutting line to separate the chips of the wafer individually. Wafer sawing process (32). The chip 21 separated from the wafer is bonded to the chip pad 11 of the lead frame 10 through the adhesive 22 and then cured-chip attach process 33. The input / output pad 21a of the chip 21 and the internal lead 12 of the lead frame 10 are connected to the gold wire 23 by capillary-a wire connection process 34. ), The package body 24 is formed and cured with an epoxy resin to protect the chip 21 from physical impact or chemical change from the outside-a mold 35. The resin impurities flowing into the outer lead 13 of the lead frame 10 are removed to facilitate the subsequent plating process-deflash process 36, the surface of the outer lead 13 is the outer lead 13 It is plated by solder 25 to prevent corrosion, to improve conductivity, and to solder to the main substrate-a plating process 37. Then, information about the package is printed on the package body 24-unnecessary parts such as the printing process 38 (mark), the outer part 15 of the lead frame 10 and the dam bar 14 are cut and removed. The manufacture of the package 20 is completed by bending the shape of the outer lead 13 so that the package can be mounted on the main substrate in an independent form-a trim / form 39.

However, the deflash process 36 and the plating process 37 require additional input of manpower, equipment, materials, etc., and also require a wastewater treatment facility for treating wastewater of chemicals generated in the processes. do. Therefore, recently, in order to omit the de-flashing process 36 and the plating process 37, a lead frame which has already been plated in the lead frame 10 manufacturing step before being introduced into the package 20 manufacturing process is developed and used. Doing. The lead frame preplated in this manner is called a pre-plated frame (PPF). Hereinafter, it will be referred to as a 'pre-plated lead frame'.

The pre-plated lead frames currently used include palladium (Pd) and nickel (Ni) plating layers. 4 is a cross-sectional view showing the layer structure of the palladium / nickel pre-plated lead frame 40, in which a plurality of plating layers 46 are formed on the lead frame skeleton layer 41. As shown in FIG. First, nickel 42 is plated on the entire surface of the lead frame skeleton layer 41, and then palladium 44 is plated. The palladium 43 strike layer may be thinly plated between the nickel layer 42 and the palladium layer 44, and a gold 45 flash layer may be formed on the palladium layer 44. It may be. Each plating layer 46 is formed over the lead frame framework layer 41, as shown in FIG. That is, not only the external lead 41c but also the chip pad 41a and the internal lead 41b are formed.

The reason why the palladium / nickel pre-plated lead frame 40 has various plating layers 46 is as follows. FIG. 5 shows a semiconductor chip package 47 using the palladium / nickel pre-plated lead frame 40 of FIG. 4. Referring to FIGS. 4 and 5, the external lead 41c of the lead frame 40 is illustrated. Is mediated between the package 47 and the main substrate (not shown) after fabrication of the package 47. At this time, the bonding between the external lead 41c and the main substrate is made through solder, which is an alloy of lead (Pb) and tin (Sn). However, since the adhesion between the solder and nickel is not good, the palladium layer 44 should be further formed on the nickel layer 42. The palladium strike layer 43 is a layer formed to mediate good adhesion between the nickel layer 42 and the palladium layer 44, and the gold flash layer 45 is formed to compensate for bonding with the solder. to be. At least the nickel layer 42 and the palladium layer 44 are necessary, so that an increase in the plating layer 46 constituting the lead frame 40 is inevitable.

The pre-plated lead frame 40, as described above, has the advantage that the de-flash process and the plating process is omitted, but also has the following problems. First, the palladium / nickel pre-plated lead frame 40 is applicable only to a copper (Cu) lead frame among conventional lead frames, and not to an iron / nickel lead frame. . If applied to an iron / nickel alloy lead frame, it should be copper plated before nickel and palladium. In other words, copper is required to plate nickel and palladium. The reason for this is as shown from the standard electrode potential of each metal shown in Table 1 below, rather than the potential difference (0.650 V) between palladium (Pd) and copper (Cu). This is because the potential difference (1.427V / 1.237V) between Ni) is much larger.

Metal-Metal Ions Standard Electrode Potential E ° (volt) Pd-Pd ⁺² +0.987 Cu-Cu ⁺² +0.337 Pb-Pb ⁺² -0.126 Sn-Sn ⁺² -0.136 Ni-Ni ⁺² -0.250 Fe-Fe ⁺² -0.440

If the potential difference between the plating layer 46 and the lead frame skeleton layer 41 is large, corrosion of the lead frame skeleton layer 41 occurs more easily. Therefore, a palladium / nickel plating layer is formed on the lead frame of the iron / nickel alloy.

In addition, since nickel and palladium are ten times greater in strength, cracks may occur in the external lead during the cutting / bending process, and may cause defects in the solder joint test. The high strength of nickel and palladium also causes the connection to be degraded during wire connection, so that the temperature of the heater block, the equipment used for wire connection, needs to be increased, or the capillary wear cycle is accelerated. There is a problem.

Therefore, an object of the present invention is to provide a lead frame for simplifying a package manufacturing process and improving productivity.

It is another object of the present invention to provide a pre-plated lead frame in which the number of plated layers of the lead frame is reduced while the reliability of wire bonding, solder bonding, etc. is improved.

It is still another object of the present invention to expand the applied material of the pre-plated lead frame and to reduce the manufacturing cost.

1 is a plan view showing an example of a lead frame according to the prior art,

2 is a cross-sectional view taken along line II-II of FIG. 1 as an example of a conventional semiconductor chip package manufactured using the lead frame of FIG.

3 is a flow chart showing a schematic manufacturing process for manufacturing the semiconductor chip package of FIG.

4 is a cross-sectional view showing a layer structure of a palladium / nickel pre-plated lead frame according to the prior art;

FIG. 5 is a cross-sectional view illustrating a semiconductor chip package using the palladium / nickel pre-plated lead frame of FIG. 4; FIG.

6 is a cross-sectional view showing a layer structure of a solder pre-plated lead frame according to the present invention;

FIG. 7 is a cross-sectional view illustrating a semiconductor chip package using the solder pre-plated lead frame of FIG. 6. FIG.

8 is a flowchart illustrating a schematic manufacturing process of the semiconductor chip package illustrated in FIG. 7;

9 is a configuration diagram of an in-line manufacturing apparatus for continuously performing the package manufacturing process of FIG. 8;

10A and 10B are diagrams showing a temperature test result;

11A and 11B are diagrams showing vibration test results.

Explanation of symbols for the main parts of the drawings

10, 40: lead frame 11, 41a: chip pad

12, 41b: inner lead 13, 41c: outer lead

14: dam bar 20, 47: semiconductor chip package

21: semiconductor chip 22: adhesive

23: Au wire 24: Package body

25 solder plating layer 30 package manufacturing process

41: lead frame skeleton layer 42: nickel (Ni) plating layer

44: Palladium (Pd) plating layer

50: solder pre-plated lead frame (solder PPF)

51: lead frame skeleton layer 51a: chip pad

51b: internal lead 51c: external lead

52: solder plating layer 53: semiconductor chip

54: adhesive 55: gold wire

56: package body 57: semiconductor chip package

60: package manufacturing process

70: package in-line manufacturing apparatus

In order to achieve the above object, the present invention provides a solder pre-plated lead frame in which a solder plating layer is formed on a surface of an external lead. The lead frame includes a chip pad to which the semiconductor chip is mechanically bonded, a plurality of internal leads arranged around the chip pad and electrically connected to the semiconductor chip and encapsulated inside the package body, and connected to the internal leads, respectively. A plurality of external leads protruding to the outside and a dam bar for connecting each of the external leads along the outside of the package body. The lead frame is made of copper or a copper alloy or an alloy of iron and nickel.

Such solder pre-plated lead frames can be used in the manufacture of semiconductor chip packages. The method for manufacturing a semiconductor chip package according to the present invention using a solder pre-plated lead frame includes a wafer attaching process in which a tape is attached to a back side of a wafer on which a plurality of semiconductor chips are formed, and a plurality of semiconductor chips along a cutting line of the wafer. A wafer cutting process to be separated, a chip bonding process in which a solder pre-plating lead frame in which a solder plating layer is formed on a surface of external leads is supplied, and a semiconductor chip separated from the wafer is bonded to a chip pad of the lead frame and cured; And a wire connection process in which the inner leads of the lead frame are connected with gold wires, and a molding process in which a semiconductor chip, a chip pad, internal leads and gold wires are encapsulated inside a package body formed of an epoxy resin along a dam bar of the lead frame, And cutting / bending in which the dam bar of the lead frame is cut off and the outer leads are bent. It includes forward.

In addition, the method of manufacturing a package using the solder pre-plated lead frame according to the present invention may further include a printing process in which information about the package is printed on the package body after the molding process is completed. In particular, the series of processes from the wafer attach process to the cutting / bending process can be carried out continuously through an in-line apparatus, and is preferable.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention. Like numbers refer to like elements throughout.

6 is a cross-sectional view showing the layer structure of the solder pre-plated lead frame 50 according to the present invention. Referring to FIG. 6, the solder plating layer 52 is formed on the surface of the skeleton layer 51 of the lead frame. Unlike the conventional palladium / nickel pre-plated lead frame, the solder pre-plated lead frame 50 is not limited to the material of the lead frame skeleton layer 51. That is, the solder is an alloy in which the mixing ratio of tin (Sn) and lead (Pb) is about 85 (± 10): 15 (± 10), and copper (Cu), which is used as a material for a conventional lead frame, Since all Cu alloys or iron / nickel alloys (Fe / Ni alloy or alloy 42) have sufficiently small potential differences (see Table 1), all three of these materials are the lead of the solder pre-plated lead frame 50. It can be used as a material of the frame skeleton layer 51.

In addition, the solder plating layer 52 may be formed only on an external lead portion of the lead frame 50 by partially using a mask in manufacturing the lead frame 50. FIG. 7 is a cross-sectional view illustrating a semiconductor chip package 57 using the solder pre-plated lead frame 50 of FIG. 6. 6 and 7, when the solder pre-plated lead frame 50 is used to manufacture the package 57, the external lead (13 in FIG. 2) by the plating process of the conventional package manufacturing process The same effect as the solder layer (25 of FIG. 2) is plated only at the site.

However, when the solder layer 25 is formed through a separate plating process after molding the package body 24 as in the conventional case, the solder layer 25 is not only used as the external lead 13 because it is difficult to use a mask. It is also formed in the outer part 15 of the lead frame 10 (refer FIG. 1 and FIG. 2). Since the lead frame outer portion (15 in FIG. 1) is an unnecessary part to be removed after the package is manufactured, the solder is wasted as much. On the other hand, in the case of the solder layer 52 of the present invention, since the solder layer 52 necessary only for the external lead 51c portion can be formed by using a mask in manufacturing the lead frame 50, the amount of solder used is reduced. Therefore, the manufacturing cost is reduced.

Moreover, since the solder plating layer 52 is formed in advance before the lead frame 50 is introduced into the package 57 manufacturing, the desplash in the manufacturing of the package 57 using the solder pre-plating lead frame 50 of the present invention. There is no need for the process and plating process. Since the deflash process is a process of removing resin impurities in order to smoothly perform the plating process, if the plating process is omitted, the deflash process may naturally be omitted. And if the de-flash process and the plating process is omitted, there is no need for a process using chemicals, thereby eliminating the wastewater treatment problem. In addition, there is an advantage to in-line package manufacturing processes. This will be described later.

In the solder pre-plating lead frame 50, the solder plating layer 52 is formed only on the outer lead 51c, and is not formed on the chip pad 51a and the inner lead 51b. Therefore, the connection between the inner lead 51b and the gold wire 55 is not affected at the time of wire connection. On the contrary, since the melting point of the solder is 197 ° C, which is lower than other metals, the temperature of the heater block, the temperature of the molding die, the pressure, and the like can be reduced.

As described above, the pre-plated lead frame 50 of the present invention is the same as the conventional lead frame structure except that the solder plating layer 52 is plated on the outer lead 51c of the lead frame 50. That is, the chip pad 51a to which the semiconductor chip 53 is mechanically bonded by the adhesive agent 54 is arranged around the chip pad 51a, and the semiconductor chip 53 is electrically connected, and the package body 56 is connected. A plurality of inner leads 51b encapsulated therein, a plurality of outer leads 51c connected to the inner leads 51b and protruding out of the package body 56, and an outline of the package body 56 are provided. And a dam bar (not shown) which connects the respective external leads 51c with each other. However, the solder plating layer 52 is not formed after the package body 56 is formed, but is characterized in that it is formed in the lead frame 50 manufacturing step. The manufacturing process 60 when such a solder pre-plated lead frame 50 is used for manufacturing the semiconductor chip package 57 is schematically shown in FIG.

Referring to FIG. 8, a wafer is subjected to a wafer attaching process 61 in which a tape is attached to a back surface of a wafer on which a plurality of semiconductor chips are formed, and a wafer cutting process 62 in which semiconductor chips are individually separated along a cutting line of the wafer. The semiconductor chip is separated from the solder lead-plated lead frame in which the solder plating layer is formed on the surface of the external leads, and the chip bonding process 63 is performed in which the semiconductor chip is bonded and cured to the chip pad of the lead frame. Subsequently, the wire connecting step 64 in which the semiconductor chips and the inner leads of the lead frame are connected with gold wires, and the semiconductor chip and the chip pads and the inner leads and the gold inside the package body formed of an epoxy resin along the dam bar of the lead frame. The package is completed by sequentially performing the molding process 65 in which the wire is enclosed and the cutting / bending process 67 in which the dam bars of the lead frame are cut and removed and the external leads are bent. On the other hand, after the molding process is completed may further include a printing process 66, the information on the package is printed on the package body. As described above, in the manufacturing 60 of the package using the solder pre-plated lead frame, the conventional deflash process 36 and the plating process 37 as shown in FIG. 3 are unnecessary.

Such a series of package manufacturing processes 60 may be performed continuously through an in-line apparatus. That is, as shown in FIG. 9, the in-line device 70 includes a wafer cutting device 71, a chip bonding device 72 including a supply of the lead frame 50, an adhesive curing device 73, and a wire. The connecting device 74, the molding device 75, the epoxy resin curing device 76, the printing device 77, the cutting / bending device 78, and the like are continuously arranged. In the conventional case, since the deflashing process and the plating process require a chemical treatment process, a washing process, and the like, automation is difficult, and thus, it is difficult to in-line. On the other hand, the present invention is easy to in-line because there is no de-flash process and plating process. 'In-line' refers to connecting each connection between devices that perform each process via a transfer rail so that each process can be done continuously and automatically.

10A and 10B show test results of measuring solder joint strength before and after a temperature test after solder bonding a package using a conventional pre-plated lead frame and a pre-plated lead frame of the present invention to a main substrate. The figure shown. 11A and 11B show the vibration test results. In each figure, (a), (b) and (c) on the horizontal axis indicate the standard type and the non-standard type of the solder pre-plated lead frame of the present invention and the conventional palladium / nickel pre-plated lead frame, respectively. The numerical value on the vertical axis represents the outer lead tensile strength of the solder joint. The unit of tensile strength is lbf (pound force). Reference numerals 81 and 11 in FIG. 10 denote packages of 60QFP type, 82 and 92 denote packages of 30SOP type, and 83 and 93 denote packages of 28SSOP type, respectively.

The temperature test of FIG. 10 repeats a temperature change from 0 ° C. to 100 ° C. 500 times for 15 minutes, and the vibration test of FIG. 11 vibrates by 125 mils (3.175 mm) at a frequency of 83 Hz for 24 hours. In the case of the conventional palladium / nickel pre-plated lead frame, since several plating layers exist, harsh treatment tests are performed at high temperature and high humidity in order to evaluate the reliability in manufacturing the lead frame. The non-standard type (C) of the palladium / nickel pre-plated lead frame refers to a lead frame that has been subjected to harsh processing tests.

As shown in FIGS. 10 and 11, the package using the solder pre-plated lead frame of the present invention, regardless of the package form, is always before or after the test compared to the package using the conventional palladium / nickel pre-plated lead frame. Tensile strength is greater. That is, the solder joint between the outer lead of the package and the main substrate is excellent.

As described above, the package using the solder pre-plated lead frame of the present invention has the following advantages over the conventional package in which the solder plating is made at the time of package manufacture. 1) Since there is no need for de-flash process and plating process, manpower, equipment and materials are saved. In particular, waste water treatment facilities are not required and environmental problems can be improved. 2) Since the solder plating layer can be formed as necessary only on the outer lead of the lead frame, the use of solder is reduced and manufacturing cost is reduced.

In addition, the solder pre-plated lead frame of the present invention has the following advantages over the conventional palladium / nickel pre-plated lead frame. 1) Since the potential difference between the solder and the lead frame material copper or iron / nickel alloy is small, the reliability is excellent and the solder plating layer can be formed regardless of the material of the lead frame. 2) Excellent solder bonding between the external lead of the package and the main board. 3) Since solder strength is lower than that of palladium / nickel, reliability is improved during cutting / bending process and connection is improved when wire is connected. 4) Since the melting point of the solder is relatively low, the curing temperature at the time of chip bonding, the heater block temperature at the time of wire connection, and the mold temperature at the time of molding can be reduced.

In particular, in manufacturing a package using a solder pre-plated lead frame, there is an advantage that the manufacturing process of the package can be performed continuously and automatically through the in-line apparatus.

Claims (8)

A chip pad to which a semiconductor chip is mechanically bonded, a plurality of internal leads arranged around the chip pad and electrically connected to the semiconductor chip and enclosed in a package body, and connected to the internal leads, respectively, and the package A semiconductor chip comprising a plurality of external leads protruding out of the body, and a dam bar for connecting the respective external leads to each other along the outer periphery of the package body, the solder plating layer is formed on the surface of the external lead Lead frame of the package. The lead frame of a semiconductor chip package according to claim 1, wherein the lead frame is made of copper or a copper alloy. The lead frame of a semiconductor chip package according to claim 1, wherein the lead frame is made of an alloy of iron and nickel. (a) a wafer attaching process in which a tape is attached to a back side of a wafer on which a plurality of semiconductor chips are formed; (b) a wafer cutting process in which the semiconductor chips are individually separated along a cutting line of the wafer; (c) a chip pad, a plurality of internal leads arranged around the chip pad, a plurality of external leads respectively connected to the internal leads, and a connection portion of each of the internal leads and the external leads to each other; And a dam bar for connecting, and a solder pre-plating lead frame having a solder plating layer pre-formed on a surface of the external leads, wherein the semiconductor chip separated from the wafer is bonded to the chip pad of the lead frame and cured. Process; (d) a wire connection step of connecting the semiconductor chip and internal leads of the lead frame with gold wires; (e) a molding process in which the semiconductor chip, the chip pad, the inner leads and the gold wire are encapsulated in a package body formed of an epoxy resin along a dam bar of the lead frame; And (f) a cutting / bending process in which the dam bars of the lead frame are cut and removed, and the external leads are bent; Method of manufacturing a semiconductor chip package using a solder pre-plated lead frame comprising a. The method of manufacturing a semiconductor chip package using a solder pre-plated lead frame according to claim 4, wherein the lead frame is made of copper or a copper alloy. The method of manufacturing a semiconductor chip package using a solder pre-plated lead frame according to claim 4, wherein the lead frame is made of an alloy of iron and nickel. The method of manufacturing a semiconductor chip package using a solder pre-plating lead frame according to claim 4, wherein the printing process of printing the information on the package is performed on the package body after the forming process (e) is completed. 5. The semiconductor according to claim 4, wherein a series of processes from (a) the wafer attaching process to (f) the cutting / bending process are performed continuously through an in-line device. Method of manufacturing the chip package.