JPH09237849A - Manufacture of semiconductor package - Google Patents
Manufacture of semiconductor packageInfo
- Publication number
- JPH09237849A JPH09237849A JP4266796A JP4266796A JPH09237849A JP H09237849 A JPH09237849 A JP H09237849A JP 4266796 A JP4266796 A JP 4266796A JP 4266796 A JP4266796 A JP 4266796A JP H09237849 A JPH09237849 A JP H09237849A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring
- semiconductor
- package
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケ−ジ
の製造法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor package.
【０００２】[0002]
【従来の技術】半導体の集積度が向上するに従い、入出
力端子数が増加している。従って、多くの入出力端子数
を有する半導体パッケージが必要になった。一般に、入
出力端子はパッケージの周辺に一列配置するタイプと、
周辺だけでなく内部まで多列に配置するタイプがある。
前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇ
ｅ）が代表的である。これを多端子化する場合は、端子
ピッチを縮小することが必要であるが、０．５ｍｍピッ
チ以下の領域では、配線板との接続に高度な技術が必要
になる。後者のアレイタイプは比較的大きなピッチで端
子配列が可能なため、多ピン化に適している。従来、ア
レイタイプは接続ピンを有するＰＧＡ（Ｐｉｎ Ｇｒｉ
ｄ Ａｒｒａｙ）が一般的であるが、配線板との接続は
挿入型となり、表面実装には適していない。このため、
表面実装可能なＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａ
ｙ）と称するパッケージが開発されている。2. Description of the Related Art As the degree of integration of semiconductors increases, the number of input / output terminals increases. Therefore, a semiconductor package having a large number of input / output terminals is required. Generally, I / O terminals are arranged in a line around the package,
There is a type that arranges not only the periphery but also the interior in multiple rows.
The former is a QFP (Quad Flat Package).
e) is representative. In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in the region of 0.5 mm pitch or less, advanced technology is required for connection with a wiring board. The latter array type is suitable for increasing the number of pins because the terminals can be arranged at a relatively large pitch. Conventionally, the array type is a PGA (Pin Gri) having connection pins.
d Array) is common, but the connection with the wiring board is of an insertion type and is not suitable for surface mounting. For this reason,
Surface mountable BGA (Ball Grid Array)
A package called y) has been developed.
【０００３】一方、電子機器の小型化に伴って、パッケ
ージサイズの更なる小型化の要求が強くなってきた。こ
の小型化に対応するものとして、半導体チップとほぼ同
等サイズの、いわゆるチップサイズパッケージ（ＣＳ
Ｐ； Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）が提案さ
れている。これは、半導体チップの周辺部でなく、実装
領域内に外部配線基板との接続部を有するパッケージで
ある。具体例としては、バンプ付きポリイミドフィルム
を半導体チップの表面に接着し、チップと金リード線に
より電気的接続を図った後、エポキシ樹脂などをポッテ
ィングして封止したもの（ＮＩＫＫＥＩ ＭＡＴＥＲＩ
ＡＬＳ ＆ ＴＥＣＨＮＯＬＯＧＹ ９４．４，Ｎｏ．
１４０，ｐ１８−１９）や、仮基板上に半導体チップ及
び外部配線基板との接続部に相当する位置に金属バンプ
を形成し、半導体チップをフェースダウンボンディング
後、仮基板上でトランスファーモールドしたもの（Ｓｍ
ａｌｌｅｓｔ Ｆｌｉｐ−Ｃｈｉｐ−Ｌｉｋｅ Ｐａｃ
ｋａｇｅ ＣＳＰ； ＴｈｅＳｅｃｏｎｄ ＶＬＳＩ
Ｐａｃｋａｇｉｎｇ Ｗｏｒｋｓｈｏｐ ｏｆ Ｊａｐ
ａｎ，ｐ４６−５０，１９９４）などがある。[0003] On the other hand, with the miniaturization of electronic equipment, the demand for further miniaturization of the package size has increased. To cope with this miniaturization, a so-called chip size package (CS
P; Chip Size Package) has been proposed. This is a package having a connection portion with an external wiring board in the mounting area, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip, an electrical connection is made between the chip and a gold lead wire, and then epoxy resin or the like is potted and sealed (NIKKEI MATERI).
ALS & TECHNOLOGY 94.4, No.
140, p18-19), or metal bumps are formed on the temporary substrate at positions corresponding to the connection portions of the semiconductor chip and the external wiring substrate, the semiconductor chip is face-down bonded, and then transfer molded on the temporary substrate ( Sm
allest Flip-Chip-Like Pac
kage CSP; The Second VLSI
Packaging Works of Jap
an, p. 46-50, 1994).
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来提
案されている半導体パッケージの多くは、小型で高集積
度化に対応できかつパッケージクラックを防止し信頼性
に優れしかも生産性に優れるものではない。本発明は、
パッケージクラックを防止し信頼性に優れる小型の半導
体パッケ−ジの製造法を提供するものである。However, most of the semiconductor packages proposed in the prior art are small in size, capable of coping with high integration, preventing package cracks, having excellent reliability, and not excellent in productivity. The present invention
The present invention provides a method for manufacturing a small semiconductor package that prevents package cracks and is excellent in reliability.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体パッケ−
ジの製造法は、 Ａ．絶縁性基板の一表面に複数組の配線が形成されてお
り、前記配線は少なくとも半導体チップ電極と接続する
インナ−接続部及び半導体チップ搭載領域部を有すもの
であり、前記絶縁性基板には前記絶縁性基板の前記配線
が形成されている箇所であって前記インナ−接続部と導
通するアウタ−接続部が設けらる箇所に開口が設けられ
ている支持基板を準備する工程、 Ｂ．半導体チップを前記支持基板の前記配線が設けられ
ている面に搭載する工程、 Ｃ．前記半導体チップ電極を前記インナ−接続部と接続
する工程、 Ｄ．前記半導体チップの少なくとも半導体チップ電極面
を樹脂封止する工程 Ｅ．前記絶縁性基板の他の表面に前記インナ−接続部と
導通するアウタ−接続部を形成する工程 を含む半導体パッケ−ジの製造法であって、前記半導体
チップと前記支持基板を固着する絶縁性のフィルム状接
着材を前記支持基板の前記配線の半導体チップ搭載領域
部を含む半導体チップが搭載される箇所に予め仮接着
し、前記配線の必要な部分に金めっきを施した後で、前
記半導体チップと前記支持基板を前記仮接着した絶縁性
のフィルム状接着材を用いて固着する工程を順次行うこ
とを含むことを特徴とするものである。Ｅ工程は、Ａ工
程の直後、Ｂ工程の直後及びＣ工程の直後であっても良
い。A semiconductor package according to the present invention.
The manufacturing method of A. A plurality of sets of wiring is formed on one surface of the insulating substrate, and the wiring has at least an inner connection portion and a semiconductor chip mounting region portion that are connected to the semiconductor chip electrode, and the insulating substrate has A step of preparing a supporting substrate in which an opening is provided at a location where the wiring of the insulating substrate is formed and at which an outer connection section that is electrically connected to the inner connection section is provided; A step of mounting a semiconductor chip on a surface of the supporting substrate on which the wiring is provided, C. Connecting the semiconductor chip electrode to the inner connecting portion, D. Step of resin-sealing at least the semiconductor chip electrode surface of the semiconductor chip E. A method of manufacturing a semiconductor package, comprising the step of forming an outer connecting portion that is electrically connected to the inner connecting portion on the other surface of the insulating substrate, the insulating property fixing the semiconductor chip and the supporting substrate. The film-like adhesive material is temporarily preliminarily adhered to a portion of the support substrate where the semiconductor chip is mounted, including the semiconductor chip mounting area portion of the wiring, and the required portion of the wiring is plated with gold, and then the semiconductor The method further comprises sequentially performing a step of fixing the chip and the support substrate using the temporarily adhered insulating film adhesive material. Step E may be immediately after step A, immediately after step B, and immediately after step C.
【０００６】[0006]
【発明の実施の形態】絶縁性支持基板としては、ポリイ
ミド、エポキシ樹脂、ポリイミド等のプラスチックフィ
ルム、ポリイミド、エポキシ樹脂、ポリイミド等のプラ
スチックをガラス不織布等基材に含浸・硬化したもの等
が使用できる。絶縁性支持基板の一表面に複数組の配線
を形成すには、銅箔をエッチングする方法、所定の箇所
に銅めっきをする方法、それらを併用する方法等が使用
できる。絶縁性支持基板に開口を設けるには、予めパン
チングしておく、レーザ加工等により行うことができ
る。インナ−接続部と導通するアウタ−接続部は、絶縁
性支持基板開口部にハンダボール、めっき等によりバン
プ等を形成することにより作成することが出来る。BEST MODE FOR CARRYING OUT THE INVENTION As an insulating support substrate, a plastic film such as polyimide, epoxy resin or polyimide, or a substrate obtained by impregnating and curing a plastic such as polyimide, epoxy resin or polyimide in a substrate such as glass nonwoven fabric can be used. . In order to form a plurality of sets of wiring on one surface of the insulating support substrate, a method of etching a copper foil, a method of plating a predetermined portion with copper, a method of using them in combination, or the like can be used. The opening can be provided in the insulating support substrate by punching in advance, laser processing, or the like. The outer connecting portion that is electrically connected to the inner connecting portion can be formed by forming bumps or the like on the insulating support substrate opening by solder balls, plating, or the like.
【０００７】絶縁性のフィルム状接着材は、半導体チッ
プ接続のためのダイボンド材であり、化１The insulating film adhesive is a die bonding material for connecting a semiconductor chip.
【化１】 （ただし、ｎ＝２〜２０の整数を示す。）で表されるテ
トラカルボン酸二無水物（１）の含量が全テトラカルボ
ン酸二無水物の７０モル％以上であるテトラカルボン酸
二無水物と、ジアミンを反応させて得られるポリイミド
樹脂、更にエポキシ樹脂等の熱硬化性樹脂、更にシリ
カ、アルミナ、等の無機物質フィラーを含有してなるフ
ィルム状接着材が好ましい。Embedded image (However, the integer of n = 2-20 is shown.) The tetracarboxylic dianhydride whose content of the tetracarboxylic dianhydride (1) is 70 mol% or more of all the tetracarboxylic dianhydrides. And a polyimide resin obtained by reacting diamine, a thermosetting resin such as an epoxy resin, and an inorganic substance filler such as silica and alumina are preferable.
【０００８】[0008]
【実施例】図１により、本発明の一実施例について説明
する。厚さ０．０７ｍｍのポリイミド接着剤をポリイミ
ドフィルム上に両面に塗布したポリイミドボンディング
シート１に、接続端子部となる穴２をドリルで開口させ
る。本実施例ではドリル加工を用いたが、パンチ加工、
エキシマレーザ、炭酸ガスレーザ等のレーザ加工を用い
てもよい。次に、厚さ０．０１８ｍｍの銅箔（日本電解
製、商品名：ＳＬＰー１８）接着後、インナー接続部及
び外部端子までの展開配線を通常のエッチング法で形成
し、一組以上からなる配線３及び外部端子用穴２を形成
した支持基板４を準備した（図１ａ）。支持基板４の作
製方法として市販の２層（銅／ポリイミド）フレキシブ
ル基板のポリイミドをレーザ加工により外部接続端子穴
を形成する方法でもよい。次にチップが搭載されるべき
部分にダイボンドフィルム（日立化成工業株式会社製、
商品名：ＤＦ−３３５）を仮接着した（図１ｂ）。仮接
着の条件は、１６０℃、５秒、３ｋｇｆ／ｃｍ2であ
る。この後、露出しているインナー接続部に電解ニッケ
ルめっき（膜厚：５μｍ）、電解金めっき（膜厚：０．
８μｍ）６を順次施した（図１ｃ）。ここでは、電解め
っきを使用したが、無電解めっきを用いてもよい。次
に、先ほど仮接着したダイボンドテープを用いて、半導
体チップ７をコレット接着により固着した（図１ｄ）。
固着条件は、２２０℃、５秒、３００ｇｆ／ｃｍ2であ
る。次にチップ電極とワイヤーボンディング接続した。
このようにして形成したものをトランスファモールド金
型に装填し、半導体封止用エポキシ樹脂（日立化成工業
（株）製、商品名：ＣＬ−７７００）を用いて各々封止
８した（図１ｅ）。その後、配線３の接続端子部にはん
だボール９を配置し溶融させた（図１ｆ）。続いて、パ
ンチにより個々のパッケージに分離させた（図１ｇ）。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. A hole 2 to be a connection terminal portion is drilled in a polyimide bonding sheet 1 in which a polyimide adhesive having a thickness of 0.07 mm is applied on both sides of a polyimide film. Although drilling is used in this embodiment, punching,
Laser processing such as excimer laser and carbon dioxide gas laser may be used. Next, after adhering a 0.018 mm-thick copper foil (manufactured by Nippon Electrolytic Co., Ltd., trade name: SLP-18), the developed wiring to the inner connection part and the external terminal is formed by a usual etching method, and one or more sets A support substrate 4 having wirings 3 and holes 2 for external terminals was prepared (FIG. 1a). As a method of manufacturing the support substrate 4, a commercially available two-layer (copper / polyimide) flexible substrate of polyimide may be used to form external connection terminal holes by laser processing. Next, die bond film (made by Hitachi Chemical Co., Ltd.,
The product name: DF-335) was temporarily adhered (Fig. 1b). The condition of temporary adhesion is 160 ° C., 5 seconds, 3 kgf / cm 2 . After that, the exposed inner connection portion is subjected to electrolytic nickel plating (film thickness: 5 μm) and electrolytic gold plating (film thickness: 0.
8 μm) 6 in sequence (FIG. 1c). Although electrolytic plating is used here, electroless plating may be used. Next, the semiconductor chip 7 was fixed by collet bonding using the die-bonding tape which was temporarily bonded (FIG. 1d).
The fixing conditions are 220 ° C., 5 seconds, and 300 gf / cm 2 . Next, the chip electrodes were connected by wire bonding.
The thus-formed product was loaded into a transfer mold and sealed with an epoxy resin for semiconductor encapsulation (manufactured by Hitachi Chemical Co., Ltd., trade name: CL-7700) 8 (FIG. 1e). . Then, the solder balls 9 were placed on the connection terminals of the wiring 3 and melted (FIG. 1f). Subsequently, the individual packages were separated by punching (FIG. 1g).
【０００９】[0009]
【発明の効果】半導体パッケージを、 ａ．一表面には半導体チップ電極と接続するインナ−接
続部が他表面にはインナ−接続部と導通したアウタ−接
続部が設けられている支持基板を準備する工程、 ｂ．半導体チップを支持基板のインナ−接続部が設けら
れている面に半導体チップ搭載する工程、 ｃ．半導体チップ電極を基板のインナ−接続部と接続す
る工程、 ｄ．半導体チップの少なくとも半導体チップ電極面を樹
脂封止する工程 を含む工程で製造する場合、支持基板のインナー接続部
などに選択的にＮｉ／Ａｕめっきを施した後、ダイボン
ディング材により固着させる方法では、パッケージサイ
ズが小さくなるとチップとワイヤーボンディング端子と
の余裕はほとんどなくなり、ダイボンディング材を所定
の位置に固着することが困難になってくる。ダイボンデ
ィング材が位置ずれを起こしワイヤーボンディング端子
上に形成されると、金めっきとダイボンディング材との
密着性が悪いために、いわゆるパッケージクラックを引
き起こす原因となる。本発明により、ダイボンドフィル
ムを固着すべきすぐ近傍に金めっき被覆したインナー端
子を配置可能になり、結果としてパッケージクラックを
防止し信頼性の高い小型半導体パッケ−ジの製造が可能
となる。According to the present invention, a semiconductor package includes: a. A step of preparing a supporting substrate having an inner connecting portion connected to the semiconductor chip electrode on one surface and an outer connecting portion electrically connected to the inner connecting portion on the other surface; b. A step of mounting the semiconductor chip on the surface of the support substrate on which the inner connection portion is provided, c. Connecting the semiconductor chip electrode to the inner connection portion of the substrate, d. In the case of manufacturing in a process including a step of sealing at least a semiconductor chip electrode surface of a semiconductor chip with a resin, a method in which Ni / Au plating is selectively applied to an inner connection portion of a supporting substrate and then fixed by a die bonding material is used. As the package size becomes smaller, there is almost no margin between the chip and the wire bonding terminal, and it becomes difficult to fix the die bonding material at a predetermined position. When the die bonding material is displaced and is formed on the wire bonding terminal, the so-called package crack is caused due to poor adhesion between the gold plating and the die bonding material. INDUSTRIAL APPLICABILITY According to the present invention, an inner terminal coated with gold plating can be arranged in the immediate vicinity to which the die bond film is to be fixed, and as a result, package cracks can be prevented and a highly reliable small semiconductor package can be manufactured.
【図１】本発明の一実施例を説明するための、半導体パ
ッケージ製造工程を示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor package manufacturing process for explaining one embodiment of the present invention.
１ ポリイミドボンディングシート ２ 外部接続用端子穴 ３ 配線 ４ 支持基板 ５ ダイボンディングテープ ６ ニッケル／金めっき ７ 半導体チップ ８ 封止材 ９ 外部接続端子 1 Polyimide Bonding Sheet 2 External Connection Terminal Hole 3 Wiring 4 Supporting Board 5 Die Bonding Tape 6 Nickel / Gold Plating 7 Semiconductor Chip 8 Sealing Material 9 External Connection Terminal
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大畑 洋人 茨城県つくば市和台48 日立化成工業株式 会社筑波開発研究所内 (72)発明者 市村 茂樹 茨城県つくば市和台48 日立化成工業株式 会社筑波開発研究所内 (72)発明者 田口 矩之 茨城県つくば市和台48 日立化成工業株式 会社筑波開発研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroto Ohata 48 Wadai, Tsukuba City, Ibaraki Prefecture Hitachi Chemical Co., Ltd.Inside Tsukuba R & D Co., Ltd. (72) Inventor Shigeki Ichimura 48 Wadai, Tsukuba City, Ibaraki Hitachi Chemical Co., Ltd. Tsukuba R & D Laboratory (72) Inventor Noriyuki Taguchi 48 Wadai, Tsukuba City, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Tsukuba R & D Laboratory
Claims (1)
形成されており、前記配線は少なくとも半導体チップ電
極と接続するインナ−接続部及び半導体チップ搭載領域
部を有すものであり、前記絶縁性基板には前記絶縁性基
板の前記配線が形成されている箇所であって前記インナ
−接続部と導通するアウタ−接続部が設けらる箇所に開
口が設けられている支持基板を準備する工程、 Ｂ．半導体チップを前記支持基板の前記配線が設けられ
ている面に搭載する工程、 Ｃ．前記半導体チップ電極を前記インナ−接続部と接続
する工程、 Ｄ．前記半導体チップの少なくとも半導体チップ電極面
を樹脂封止する工程 Ｅ．前記絶縁性基板の他の表面に前記インナ−接続部と
導通するアウタ−接続部を形成する工程 を含む半導体パッケ−ジの製造法であって、前記半導体
チップと前記支持基板を固着する絶縁性のフィルム状接
着材を前記支持基板の前記配線の半導体チップ搭載領域
部を含む半導体チップが搭載される箇所に予め仮接着
し、前記配線の必要な部分に金めっきを施した後で、前
記半導体チップと前記支持基板を前記仮接着した絶縁性
のフィルム状接着材を用いて固着する工程を順次行うこ
とを含むことを特徴とする半導体パッケ−ジの製造法。1. A. A plurality of sets of wiring is formed on one surface of the insulating substrate, and the wiring has at least an inner connection portion and a semiconductor chip mounting region portion that are connected to the semiconductor chip electrode, and the insulating substrate has A step of preparing a supporting substrate in which an opening is provided at a location where the wiring of the insulating substrate is formed and at which an outer connection section that is electrically connected to the inner connection section is provided; A step of mounting a semiconductor chip on a surface of the supporting substrate on which the wiring is provided, C. Connecting the semiconductor chip electrode to the inner connecting portion, D. Step of resin-sealing at least the semiconductor chip electrode surface of the semiconductor chip E. A method of manufacturing a semiconductor package, comprising the step of forming an outer connecting portion that is electrically connected to the inner connecting portion on the other surface of the insulating substrate, the insulating property fixing the semiconductor chip and the supporting substrate. The film-like adhesive material is temporarily preliminarily adhered to a portion of the support substrate where the semiconductor chip is mounted, including the semiconductor chip mounting area portion of the wiring, and the required portion of the wiring is plated with gold, and then the semiconductor A method of manufacturing a semiconductor package, which comprises sequentially performing a step of fixing a chip and the support substrate using the temporarily adhered insulating film adhesive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04266796A JP3599142B2 (en) | 1996-02-29 | 1996-02-29 | Manufacturing method of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04266796A JP3599142B2 (en) | 1996-02-29 | 1996-02-29 | Manufacturing method of semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09237849A true JPH09237849A (en) | 1997-09-09 |
| JP3599142B2 JP3599142B2 (en) | 2004-12-08 |
Family
ID=12642381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04266796A Expired - Lifetime JP3599142B2 (en) | 1996-02-29 | 1996-02-29 | Manufacturing method of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3599142B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100379086B1 (en) * | 1998-10-31 | 2003-07-18 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package Manufacturing Method |
-
1996
- 1996-02-29 JP JP04266796A patent/JP3599142B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100379086B1 (en) * | 1998-10-31 | 2003-07-18 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package Manufacturing Method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3599142B2 (en) | 2004-12-08 |
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