JPS63186455A - Package for semiconductor - Google Patents
Package for semiconductorInfo
- Publication number
- JPS63186455A JPS63186455A JP1793187A JP1793187A JPS63186455A JP S63186455 A JPS63186455 A JP S63186455A JP 1793187 A JP1793187 A JP 1793187A JP 1793187 A JP1793187 A JP 1793187A JP S63186455 A JPS63186455 A JP S63186455A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- sealing
- semiconductor
- silver
- pps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000007789 sealing Methods 0.000 claims abstract description 25
- 239000004734 Polyphenylene sulfide Substances 0.000 claims abstract description 13
- 229920000069 polyphenylene sulfide Polymers 0.000 claims abstract description 13
- 229910052709 silver Inorganic materials 0.000 claims abstract description 6
- 239000004332 silver Substances 0.000 claims abstract description 6
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical group [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 229920005992 thermoplastic resin Polymers 0.000 claims description 4
- 229920005989 resin Polymers 0.000 abstract description 8
- 239000011347 resin Substances 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 7
- 238000007747 plating Methods 0.000 abstract description 4
- 230000004927 fusion Effects 0.000 abstract description 3
- 239000002344 surface layer Substances 0.000 abstract description 2
- 238000003466 welding Methods 0.000 abstract 2
- 238000003825 pressing Methods 0.000 abstract 1
- 229920001169 thermoplastic Polymers 0.000 abstract 1
- 239000004416 thermosoftening plastic Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 12
- 238000004381 surface treatment Methods 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 AgzO Chemical class 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 1
- 229910052946 acanthite Inorganic materials 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- QRJOYPHTNNOAOJ-UHFFFAOYSA-N copper gold Chemical compound [Cu].[Au] QRJOYPHTNNOAOJ-UHFFFAOYSA-N 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000007500 overflow downdraw method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- FSJWWSXPIWGYKC-UHFFFAOYSA-M silver;silver;sulfanide Chemical compound [SH-].[Ag].[Ag+] FSJWWSXPIWGYKC-UHFFFAOYSA-M 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、熱可塑性樹脂ポリフェニレン・サルファイド
（以下ＰＰＳと略す）を用いた半導体用パッケージにお
いて、使用するリードフレームの材質と表面処理に関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the material and surface treatment of a lead frame used in a semiconductor package using thermoplastic resin polyphenylene sulfide (hereinafter abbreviated as PPS).
（従来の技術）
従来、半導体、特に集積回路の封止に用いられて来た材
質は、シェルとしては、セラミックかエポキシ系の封止
材が使わｎ％Ｕ−ド・フレーム材としては、表−１に示
すものに代表さｎて来た。(Prior art) Conventionally, materials used for encapsulating semiconductors, especially integrated circuits, include ceramic or epoxy encapsulating materials for the shell, and n%U-doped frame materials. -1 is representative.
表−１リード・フレーム材
リードフレームは、ダイボンティング部とワイヤ・ポン
ディングのみ、銀又は金の部分めっきをほどこし、封止
面は無めっきのままかはとんどである。Table 1 Lead frame materials The lead frame is partially plated with silver or gold only at the die bonding part and wire bonding, and the sealing surface is mostly left unplated.
（発明が解決しようとする問題点）
熱可塑性樹脂ＰＰＳを用いて、半導体果梗回路の封止を
行おうとする時、一つの方法として、あらかじめ、上、
下のシェルをそれぞれ成形し、リードフレームｔ−はさ
み込む封止面だけ、封止時熱溶融させ、加圧融着する封
止方法が考えられる。(Problems to be Solved by the Invention) When attempting to seal a semiconductor circuit using a thermoplastic resin PPS, one method is to seal the top,
A conceivable sealing method is to mold the lower shells respectively, heat-melt only the sealing surfaces sandwiching the lead frame T, and press-fuse them during sealing.
この方法を実施する時、従来、セラミツクツ（ッケージ
又はエポキシ封止品で用いらｔて米たリードフレーム材
と表面処理法をそのまま適用しても、うｆく行かない。When carrying out this method, it will not work if the lead frame materials and surface treatment methods conventionally used in ceramic packaging or epoxy encapsulation products are applied as they are.
但し、ここでいう封止性良否の判定は、ＭＩＬ−８ＴＤ
７５０ＣＭｅｔｈｏｄ １０７１ 、２ ｃｏ１４ｄ、
ＤＫＭ格化さｎているグロスリークテスト（Ｇｒｏｓｓ
Ｌｅａｋ Ｔｅ５ｔ、以下ｑｔテストと略す）によっ
た。However, the judgment of sealing quality here is based on MIL-8TD.
750CMethod 1071, 2 co14d,
DKM standard gross leak test (Gross
Leak Te5t (hereinafter abbreviated as qt test).
本発明においては、ＰＰＳ樹脂を用いた熱融着方式、半
導体封止法において、良好な封止性を得るために、リー
ドフレーム材質と表面処理について、種々実験を行い、
良い結果を得る条件を選び出した。In the present invention, in order to obtain good sealing performance in the heat fusion method and semiconductor sealing method using PPS resin, various experiments were conducted on the lead frame material and surface treatment.
We have selected conditions that will yield good results.
（問題点を解決するための手段）（実施例〕第１図げ）
を工、本件のＰＰＳ樹脂を用いた半導体パッケージの封
止前の各部分の関係を示し、第１図（ロ）は封止後の状
態を示す。いずわも、模式的に示した断面図である。第
１図ビ）（ロフにおいて、１，１′は上側シェル、２，
２′は下側シェル５，６′＆’Ｓ Ｅ Ｐ ＲＯＭ （
Ｅｖａｓａｂｌｅ Ｐｒｏｇｒａｍｍａｂ ｌｅ Ｒｅ
ａｄＯｎｌｙ Ｍｅｍｓｒｙ）に使われる紫外＃ｉｔａ
過型のガラス・リッドである。４，４′はリードフレー
ム、５゜５′は半導体チップ、６，６′はボンティング
ワイヤテする。封止後、リードフレーム４′のシェル１
′。(Means for solving problems) (Example) Figure 1)
Figure 1(b) shows the relationship between the various parts of the semiconductor package using the PPS resin of the present invention before sealing, and FIG. 1(b) shows the state after sealing. This is a schematic cross-sectional view. Figure 1 B) (In the lof, 1, 1' are the upper shell, 2,
2' is the lower shell 5, 6'&'S E P ROM (
Evasable Programmable Re
UV #ita used for adOnly Memsry)
It has an oversized glass lid. 4, 4' are lead frames, 5° 5' are semiconductor chips, and 6, 6' are bonding wires. After sealing, shell 1 of lead frame 4'
'.
２′から外部にはみ出した部分は、余分なつなぎ部分は
カットさｎ（図示せず）、外部リードとなる部分Ｌ Ｌ
ｅｎｄ） は曲げらｎて、第１図（ロ）Ｋ示す形状と
なる。For the part that protrudes from 2', cut off the excess connecting part (not shown), and cut off the part that will become the external lead L L
end) is bent to take the shape shown in FIG. 1(b)K.
第１図イ）に示す封止を行うには、上側シェル１と下側
シェル２のリード２レーム４に接する面の表層を熱風に
て浴かし、あらかじめ加熱してあったチップ付リード２
−ムをはさみ込む形で加圧熱融着を行う。To perform the sealing shown in FIG.
- Pressure and heat fusion is performed by sandwiching the film.
良好な封止性を得るために、表−２に示すごときリード
フレーム材と表面処理の組合せで、封止実験を行ったが
、結果は、鋼糸のリードフレームに鋏めっきをほどこし
た場合のみに良好な結果が得らｎた。In order to obtain good sealing performance, sealing experiments were conducted using the combinations of lead frame materials and surface treatments shown in Table 2, but the results were only obtained when scissor plating was applied to the steel thread lead frame. Good results were obtained.
以下余白
表−２９−トフレーム材とめっき内組台せにょる封止性
○印 封止性良好
×印 封止性悪い
−未実施
（作用〕
ＰＰＳ樹脂と銅系台金リードフレームの銀めっき品との
組付せの場合のみ良好な封止性が得らｎる理由は必ずし
も明確でないが、
（１） ＰＰ５Ｉ（脂の浴融から固化に至る過程で、
熱収縮が起るが、この時、勝＃５Ｂ係数がＰＰ５Ｖｃ近
い、リードフレーム材の方が、収縮応力が小さくてすむ
。Below is a margin table - 29 - Sealing property of frame material and plating inner assembly stand ○ mark Good sealing property × mark Bad sealing property - Not implemented (effect) Silver plating of PPS resin and copper base metal lead frame The reason why good sealing performance is obtained only when assembled with products is not necessarily clear, but (1) PP5I (in the process from bath melting to solidification of fat,
Heat shrinkage occurs, but at this time, lead frame materials with a win #5B coefficient close to PP5Vc have smaller shrinkage stress.
（２ＪＰＰＳ樹脂と銀めっき面との間に、何らかの化学
結合が行わｎる。(2) Some chemical bonding occurs between the JPPS resin and the silver-plated surface.
等が考えらｎろ。（υの理由については、使用したＰＰ
５ｆｌｔ４脂］線膨張係数＆Ｘ２３ Ｘ １０−’／℃
であり、リードフレーム材Ａ１１ｏｙ４２に比べれば、
０１ｉｎ１９４並びにＭＰ−２０２の線膨張係数は、を
よるかに近い。（２）の理由については、銀めっき面の
オージェ分析並びにＥＳＣＡ分析（Ｅｌｅｃｔｒｏｎ
５ｐｅｃｔｒｏｓｃｏｐｙ ｆｑｒ Ｃｈｅｍｉｃａｌ
Ａｎａｌｙｓｉｓ）の結果、表面にＡｇ２Ｓ ｙ、ＪＺ
ＡｇｚＯ等の化付物が存在するＳ曾は封止性が恩く、
汚ｎのから推定すると、ＰＰＳ樹脂のＳ元素側鎖とリー
ドフレーム表面のＡｇ元素との結合が起きていることも
考えらねる。I can't think of anything like that. (For the reason for υ, please refer to the PP used
5flt4 fat] Linear expansion coefficient &X23 X 10-'/℃
And compared to lead frame material A11oy42,
The linear expansion coefficients of 01in194 and MP-202 are very close. Regarding the reason (2), Auger analysis and ESCA analysis (Electron
5pectroscopy fqr Chemical
As a result of analysis), Ag2S y, JZ
S, which has chemical compounds such as AgzO, has good sealing properties.
Judging from the amount of contamination, it is inconceivable that bonding occurs between the S element side chain of the PPS resin and the Ag element on the surface of the lead frame.
（発明の効果〕
ＰＰＳ樹脂を用いたあらかじめ成形さｎた上下のシェル
のリードフレームをはさみ込む場合に、その封止面表層
を熱風にて短時間浴融させ、別途加熱さｎたチップ付リ
ードフレームを同時に上下のシェルではさみ込む半導体
用パッケージにおいては、使用するリードフレーム材金
銅系合金とし、表面金銀めっきした時のみ、良好な封止
結果が得らｎた。(Effect of the invention) When sandwiching lead frames of upper and lower shells pre-molded using PPS resin, the surface layer of the sealing surface is melted in a bath with hot air for a short time, and the lead with a chip is separately heated. In a semiconductor package in which a frame is simultaneously sandwiched between upper and lower shells, good sealing results were obtained only when the lead frame material was a gold-copper alloy and the surface was plated with gold and silver.
第１図げ）（ロＨ工本発明で触ｆた熱司製性樹脂を用い
た半導体パーケージの構造を示す断面図である。
符号の説明
１．１′ 上側シェル ２，２′ 下側シェル６．６
′ ガラス・リッド ４，４′ リード・フレーム
５．５’ 半４体テップ ６，６′ ボンディン
グ・ワイヤ５．５′ 半導体テップ ６，６′
ホンディング・ワイヤ負へ １ 図FIG. 1 is a sectional view showing the structure of a semiconductor package using thermoplastic resin mentioned in the present invention. Explanation of symbols 1.1' Upper shell 2, 2' Lower shell 6 .6
' Glass lid 4,4' Lead frame 5.5' Half-quad tip 6,6' Bonding wire 5.5' Semiconductor tip 6,6'
Honding wire to negative 1 figure
Claims (1)
いた半導体用パッケージにおいて、リードフレームを銅
合金系とし、該リードフレームの封止面には銀めっきを
ほどこしたことを特徴とする半導体用パッケージ。(1) A semiconductor package using thermoplastic resin polyphenylene sulfide, characterized in that the lead frame is made of a copper alloy, and the sealing surface of the lead frame is silver plated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1793187A JPS63186455A (en) | 1987-01-28 | 1987-01-28 | Package for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1793187A JPS63186455A (en) | 1987-01-28 | 1987-01-28 | Package for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63186455A true JPS63186455A (en) | 1988-08-02 |
Family
ID=11957515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1793187A Pending JPS63186455A (en) | 1987-01-28 | 1987-01-28 | Package for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63186455A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0276245A (en) * | 1988-09-13 | 1990-03-15 | Mitsui Petrochem Ind Ltd | Semiconductor device and manufacture thereof |
| JPH0273744U (en) * | 1988-11-26 | 1990-06-05 | ||
| JPH04309831A (en) * | 1991-04-05 | 1992-11-02 | Fujikura Ltd | Plastic mold pressure sensor package |
-
1987
- 1987-01-28 JP JP1793187A patent/JPS63186455A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0276245A (en) * | 1988-09-13 | 1990-03-15 | Mitsui Petrochem Ind Ltd | Semiconductor device and manufacture thereof |
| JPH0273744U (en) * | 1988-11-26 | 1990-06-05 | ||
| JPH04309831A (en) * | 1991-04-05 | 1992-11-02 | Fujikura Ltd | Plastic mold pressure sensor package |
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