JPS62156697A - Integrated circuit device for driving liquid crystal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an integrated circuit device for driving a liquid crystal display device.
In particular, the present invention relates to an integrated circuit device for a liquid crystal display, which includes a RAM for storing data to be displayed on a liquid crystal, and an address setting circuit for the RAM.

[Technical background of the invention]

Liquid crystal display devices generally display images and the like by being driven by an integrated circuit device that operates in an X-Y matrix structure with a six-character drawing system. Such an integrated circuit device for driving a liquid crystal is an integrated circuit device that includes a built-in RAM for storing display data of a liquid crystal display device and also includes an address setting circuit for the RAM.

The prior art will be explained below with reference to FIGS. 3 and 4 of the accompanying drawings. FIG. 3 is a block diagram showing the configuration of a conventional integrated circuit device including a RAM and a RAM address setting circuit. The interface control circuit 1 receives a read/write (R/W) signal, a data in <D/I) signal, and 8-bit display data DBO-DB7 from a microprocessor (hereinafter referred to as MPU) not shown.

Interface control circuit 1 supplies 9-bit address information to X register circuit 2 and Y address counter circuit 3. Furthermore, the output of the Y address counter circuit 3 is connected to the MPU via the interface control circuit 1.
Display data RAM together with display data DBO to DB7
4 is supplied.

FIG. 4 is an explanatory diagram showing the address structure of the display data RAM of the prior art, and the operation when writing display data to page O and page 1 of the display data RAM 4 in the prior art will be explained using this diagram.

First, the MPU sets an X address in the X register circuit 2 to set page O of the display data RAM 4. Next, the MPU sets address 0 as the start address of the Y address in the Y address counter circuit 3. The Y address counter circuit 3 sets the Y address and automatically increments the counter by read/write operations of display data.
Increase the count by 1. As a result, the display data RAM 4 is transferred from the MPU via the interface control circuit 1.
Every time display data is written to the interface controller 1, the roll circuit 3 sequentially sets the counter from address 0 to -4-.
1 count up, O number! The display data from l (FIG. 4 AI> to address 7 (FIG. 4 A8)) are sequentially written to O page of display data [Dog ΔM4.

Next, when writing display data to the first page of the display data RAM 4, the MPU again sends the X address setting to the X register circuit 2 to set the first page of the display data RAM 4.
go to As a result, the display data RA is
Display data from address 0 (A9 in FIG. 4) to address 7 (A16 in FIG. 4) is written on one page of M4.

[Problems with background technology]

However, according to the above-mentioned conventional technology, when writing display data from O page address 0 (FIG. 71 Al> to page 1 address 7 (FIG. 4 A16) of display data RAM 4, O page The disadvantage is that when moving from page 1 to page 1 and writing display data (that is, when moving from 8 to A9 in FIG. 4), the X address must be specified in the X register circuit 2 each time. For this reason, it is difficult to display graphics on a liquid crystal display device.
The problem is that it is not possible to continuously set the address of the display data RAM.

[Object of the Invention] The present invention has been made in order to overcome the drawbacks of the above-mentioned prior art. The purpose is to provide an integrated circuit device.

(Summary of the Invention) The present invention includes an X address counter circuit and a Y address setting circuit for setting the X and Y addresses of a display data RAM.
The present invention provides an integrated circuit device for driving a liquid crystal, which is equipped with an address counter circuit and is capable of continuously setting addresses even when the addresses of the RAM are set over two or more pages.

(Embodiments of the Invention) The present invention will be described in detail below with reference to FIGS. 1 and 2 of the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment.

Is interface control circuit 1 from MPU? /
W former Ubi r'l/T Shingo Riratyji data bus information DB
O to DB7 are received and address information is supplied to the address setting circuit 5. The address setting circuit 5 includes an X address counter circuit 6 and a Y address counter circuit 3.

The output of the address setting circuit 5 is sent to the display data RAM 4 via the interface control circuit 1 (D
BO to DB7).

The operation of writing display data to page O and page 1 of the display data RAM 4 of the embodiment will be described below with reference to FIG. Note that FIG. 2 is an explanatory diagram of the operation of the prior art. FIG. 5 is an explanatory diagram corresponding to FIG. 4 and showing the address structure of the display data RAM.

First, the MPU sets O page in the X address counter circuit 6 of the address setting circuit 5. Further, the Y address counter circuit 3 is set to address 0. The X address counter circuit 6 sends the R/W signal of the MPU to the interface controller 1.
- Input via the roll circuit 1 and automatically count up the counter by +1 by read/write operations.

As a result, display data (
DBO-DB7) is the display data R set by the X address counter circuit 6 and the Y address destination 929 circuit 3.
The data will be sequentially written to predetermined addresses of AM4.

That is, first, display data is written to the O page set by the X address counter circuit 6 and the O address (A1 in FIG. 2) set by the Y address destination 929 circuit 3. Next,
The address counter circuit 6 counts up +1 address and sets one page. At this time, Y address destination 929
The address of circuit 3 is still address O, and the display data RA
Display data is written to page 1 of the X address and address O of the Y address (A2 in FIG. 2) of M4. Next, the X address counter circuit 6 counts up +1 address and addresses O page. On the other hand, the Y address destination 929 circuit 3 receives the count up completion output from the X address counter circuit 6, and increments the address by +1. As a result, the X address of the addresses set in the display data RAM 4 is O page, and the Y address is address 1 (A3 in FIG. 2). In this way, as the X address counter circuit 6 counts up, the Y address destination 929 circuit 3 counts up the address by +1, and the second
A4゜A5. ..., A15. Display data can be written to the display data RAM 4 shown at A16.

In the above embodiment, the X address counter circuit counts up first, and the Y address counter circuit 29 counts up by one count. However, the present invention is not limited to this. In addition, display data RAM
The same applies to pages and addresses where the address is 0.1 page and addresses O to 7Kr.

[Summary of the invention]

As described above, according to the present invention, since the address setting circuit of the display data RAM is provided with the X address counter circuit,
A liquid crystal driving integrated circuit that can easily and continuously set the display data RAM address with a simple configuration without the need to receive the X address setting from the MPU even when moving to a page with a different X address setting of the display data RAM. equipment can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG.
FIG. 3 is a block diagram showing the configuration of the prior art, and FIG. 4 is an explanatory diagram explaining the operation of the prior art. 1...Interface control circuit, 3...Y
Address color 29 circuits, 4...Display data RAM, 5
...Address setting circuit, 6...X address counter circuit. Applicant's agent Mr. Sato Figure 1 Figure 2

Claims (1)

[Claims] A liquid crystal drive characterized in that an address setting circuit for setting X and Y addresses of a RAM that stores display data includes an X address counter circuit and a Y address counter circuit, and the addresses of the RAM are continuously set. integrated circuit devices.