JPS62267793A - Bit map display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a bitmap display device used in microcomputer systems and the like.

<Prior Art> Currently, bitmap display devices used in microcomputer systems and the like that are capable of color display have already been developed.

This bitmap display device has three planes, each of which is configured to display red, green, and blue, and reads out the display data written to each of these planes and transfers it to the CRT. Display in color on top.

<Problems to be Solved by the Invention> However, in such conventional bitmap display devices, when displaying white characters or images on a CRT, the same display data must be sequentially written to each of these planes. Must be.

For this reason, there is a problem in that the CPU overhead increases during writing.

In view of the above circumstances, the present invention provides a bitmap display device that can simultaneously write the same display data to each plane, thereby reducing CPU overhead during writing and improving drawing speed. It is intended to.

Means for Solving the Problems> In order to solve the above problems, the bit map display device according to the present invention is a bit map display device equipped with a plurality of planes, in which a virtual plane is provided and data is stored in this virtual plane. It is characterized in that when data is written, the data is simultaneously written to a predetermined plane among the other planes.

<Embodiment> FIG. 1 is a block diagram showing an embodiment of a bitmap display device according to the present invention, and FIG. 2 is a schematic diagram showing an example of a memory map of the same embodiment.

The bitmap display device shown in this figure is a CPU
I, decoder 2, F/F (7 lip/70 lip) 3
, a gate circuit 4, and first to third planes 5 to 7. When the CPU performs a write operation once to the virtual plane 8 shown in FIG. Among them, the same display data is written to the one selected in advance.

The CPUI controls the operation of this device (
(n+1) address lines and 16 data lines.

When the CPU outputs the address signal ADO-ADn, this is supplied to each of the planes 5 to 7, and part of it (the upper few bits) is supplied to the decoder 2. In addition, the CPU 1 and the data signal DO-D15
When output, this is supplied to each plane 5 to 7, and a part of it (data signals Do to D2) is sent to the F/F.
3.

When the setting pulse CK is supplied to the F/F3, the C
In the data signals DO to D2 output by PU 1, the bits corresponding to planes 5 to 7 on which simultaneous writing is performed are set to %II, and 4 also receives the signal.
The data signal Do-D2 held here is the simultaneous write selection signal DOa.
-02a is supplied to the gate circuit 4.

Further, the decoder 2 receives the address signal ADO from the CPU 1.
- When ADn is output, if the virtual plane 8 is specified by the address signals ADO to ADn, a simultaneous write instruction signal (sII signal) SO is generated, and the address Signal ADO
If any of the planes 5 to 7 is specified by ~ADn, one of the 1.2.3 plane selection signals (%lI signal) Sl and S2.83 is generated accordingly, This is supplied to the gate circuit 4.

The gate circuit 4 includes AND gates 9 to 11 and OR gates 12 to 14, and receives the first 2.3 plane selection signal S1. S2. When any one of the planes S3 is supplied, it is supplied to the chip select terminal 'C8 of the corresponding plane among the planes 5 to 7. Further, when the simultaneous write instruction signal SO is supplied, this simultaneous write instruction signal SO and the simultaneous write selection signal D Oa = D 2 a outputted from the F/F 3 are ANDed, and this is applied to each plane 5. ~7 chip select terminals C8, respectively.

Planes 5 to 7 each have a capacity equivalent to one CRT screen, and are turned on when the 111 signal is supplied to the chip select terminal C8, and the address signal ADO
The data signal DO-D is sent to the address specified by ~ADn.
Write the display data indicated in step 15.

Next, the display data writing operation of this embodiment will be explained with reference to the flowchart shown in FIG.

First, before writing display data to each plane 5 to 7,
The CPU generates 3-bit data with the bits corresponding to the planes to be written simultaneously set to %IN, and supplies this to the F/F3 as data signals DO to D2 (step 5TI). A setting pulse CK is supplied (step ST2). F'
Data signal DO-D2 is set to /F3, and simultaneous write selection signals DOa to D2a are output from its output side.

Next, the CPUI outputs address signals ADO to ADn. In this case, if any of the planes 5 to 7 is specified by the address signals ADO to ADn (step 5T3), the decoder 2 outputs the address signals ADO to ADn. Pre-line selection signals SL, S2. Of S3, the address signal ADO-A
A signal specified by Dn is generated and supplied to the corresponding one of the planes 5 to 7 via the gate circuit 4 (step ST4).

As a result, the plane designated by the address signal ADO-ADn among the planes 5 to 7 is turned on, and the address signal ADO-AD in that plane is turned on.
The address specified by n is selected.

Next, the CPUI outputs data signals DO to D15 and writes display data to the specified address of the plane specified by the address signals ADO to ADn (step 5T5).

Further, in step ST3, the address signal ADO
-If virtual plane 8 is specified by ADn,
Decoder 2 generates simultaneous write instruction signal SO and supplies it to gate circuit 4.

From this K, the gate circuit 4 outputs this simultaneous write instruction signal S.
O and the simultaneous write selection signal D output by the F/F3.
The result is ANDed with Oa - D 2 a, and this is supplied to each of the planes 5 to 7 (step 5T6).

As a result, among the planes 5 to 7, those specified by the simultaneous write selection signal 'DOa=D2a are simultaneously turned on, and the address 1 specified by the address signals ADO to ADn in that plane is turned on. is selected.

When the CPUI outputs the data signals DO to D15, the display data is simultaneously input to the addresses specified by the address signals ADO to ADn of the planes 5 to 7 that are in the on state. In addition, during reading, the display data written in each of these planes 5 to 7 is read out sequentially, and this is read out from the CR.
The signal is supplied to a cathode ray tube display (T) and displayed.

In this embodiment, the data signals DO to D
If you specify the planes to write at the same time using 2,
When virtual plane 8 is specified, data signals DO to D2
Since the display data is simultaneously written to the planes specified in advance by , it is possible to reduce the overhead of the CPU during writing and improve the drawing speed.

<Effects of the Invention> As explained above, according to the present invention, the same display data can be written to each plane at the same time, thereby reducing the CPU overhead during writing and improving the drawing speed. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a bitmap display device according to the present invention, FIG. 2 is a schematic diagram showing an example of a memory map of the same embodiment, and FIG. 3 is a flowchart showing an example of a write operation of the same embodiment. be. 1...CPU, 2...Decoder, 3...F/F,
4... Gate circuit, 5-7... First to third planes, 8... Virtual plane.

Claims (1)

[Claims] A bitmap display device having a plurality of planes is characterized in that a virtual plane is provided, and when data is written to this virtual plane, the data is simultaneously written to a predetermined one of the other planes. A bitmap display device.