JPS5856176A - Controller for data discrimination and writing - Google Patents

Abstract

PURPOSE:To shorten the time when an image information is written in a memory, by comparing image information transmitted to the memory with picture element information through hardware, and thus discriminating whether the information can be written in the memory or not. CONSTITUTION:When an image information arrives at input terminals 1a-1h as picture element information, a signal regarding the picture element information arrives at an input terminal 6, and a comparing circuit 4 compares it with picture element information in a data register 3 to supply (1) to the other input terminal of an NAND circuit 10 when the both are completely equal. Then, a write control signal for the memory is outputted from an output terminal 12, so the picture element information is not written in the memory. When the arrival picture element information is of different kind, the circuit 4 outputs (0) and the picture element information is written in the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data identification write control device, which stores pixel information that does not need to be written into a memory in advance, and compares pixel information transmitted to the memory with this pixel information by hardware. It is an object of the present invention to provide a data identification write control device that reduces the time required to store transmitted image information in a memory by identifying whether or not it is possible to write data into the memory.

Generally, when image processing is performed by a computer, the image information for obtaining the image shown in FIG.
Write on the image information to obtain the image shown in the drawing,
Image processing such as displaying a composite image of the images shown in FIG. 1 (5), 2) as shown in FIG. In this case, in Figure 1 (5
) is written as it is in the image information storage area of FIG.
This results in the image information of the composite image shown in the figure.

For this reason, conventionally, in order to synthesize the image information of FIG. 1(q) from the image information of FIG. 1(A), 03), the image information of the direction of FIG. It identified whether it was information or background image information, and wrote only the image information of the image summer into the image information storage area of Figure 1 (b) to obtain the combined image information of Figure 1 (0). However, this method has the disadvantage that it takes a lot of time to synthesize all the mgI information of each pixel using software.

The present invention eliminates the above-mentioned drawbacks, and one embodiment thereof will be described with reference to FIG. 2 and the following figures.

For convenience of explanation, the image information for each pixel is, for example, 8
It is composed of bit pixel information, and represents colors obtained by 256 combinations of bright If and 9 hues of saturation. Also, a control signal (hereinafter referred to as 1'-MWRT signal) instructing the timing of including this pixel information is supplied to the memory, and the memory performs writing when this MWRT signal is "true" (logical "1"). .

FIG. 3 shows one of the data identification write control devices according to the present invention.
A block system diagram of an embodiment is shown. In the figure, 1a to 1h are central processing units (hereinafter referred to as OP UJ).

These are input terminals to which the first to eighth bits of pixel information from (not shown) are respectively input, and output terminals 23 to 2 are respectively input.
Figure 1 (B)
A memory (not shown) in which first image information shown in is stored.
transmitted to. In addition, the input terminals 13 to 1h are connected to the input terminals 33 to 3h of the data register 3 and the input terminals 4a to 4h of the comparison circuit 4, respectively, so that pixel information consisting of 8 bits is input to the data register. 3 and a comparison circuit 4. Also, any one of the pixel information coming in from the input terminals 13 to 1h (for example, the terminal 1a
(signals from 1 to 3) are supplied to the data terminal of the D-type flip-flop 5. In addition, the input terminal 6 receives the MWRT signal, the input terminal 7 receives the control signal (hereinafter referred to as 1'-Ilo W) LT signal that instructs the operation timing of the input/output control circuit 8, and the input terminal 9 receives signals such as the I10 address. Each OPU
(not shown).

The input/output control circuit 8 receives I 10 WH from the input terminal 7,
When the T signal is "1", the I10 address data from input terminal 9 is decoded, and this data issues a write command to the specified device (for example, flip 70 lub 5° data register 3). A signal is supplied. The flip-flop 5 switches whether the device of the present invention operates or not, and the signal of the first bit of the control information from the CPU supplied from the input terminal 1a to the data terminal is rlJ. Then, when the write command supplied to the clock terminal from the input/output control circuit 8 becomes "1", a signal of "1" is thereafter supplied from the output terminal Q to one input terminal of the NAND circuit 10, and the device of the present invention is in the operating state. Next, the data l/jimeta 3 is supplied with a write command rlJ from the input/output control circuit 8 at its control input terminal, and at the same time, the pixel information of the background (2) shown in FIG. 1 (5) is supplied to the terminals 3a to 3h. , the data register 3 stores this -+n pixel information and thereafter supplies this 8-bit pixel TFT information to the input terminal 4 of the comparison circuit 4 from the output terminals 31 to 3p.

Next, the second image information shown in FIG. 1 is input to the input terminals 1a to 1h as 8-bit 1iTII accumulated information for each pixel, and this pixel information and the information shown in FIGS. 2(A) and 2(B) are input.
A MWRT signal having the relationship shown in FIG. 1 enters the input terminal 6.

The pixel information of each pixel is compared in the comparator circuit 4 with the background pixel information from the data register 3 in the first to eighth bits, and only when the bits are all equal, the comparator circuit 4 outputs "1" to the NAND circuit 10. to the other input terminal. The output signal of this NAND circuit 1° is supplied to one input terminal of an AND circuit 11, where it is ANDed with the MWRT signal supplied to the other input terminal, and is remembered from the output terminal 12. ◎For this reason, when the pixel information coming into the input terminals 1a to 1h is equal to the pixel information of the background ① stored in the data register 3, the second The MWRT signal shown in FIG. 2(B) is output at the output terminal 12 as shown in FIG. When the incoming pixel information is that of the image!, the comparator circuit 4 outputs "0" and one input of the NAND circuit 11 is rlJ.
Therefore, the MWF shown in Fig. 2 [F]) from the input terminal 6 is
The LT signal is directly outputted from the output terminal 12 with the waveform shown in FIG. 2 ([3), and the pixel information of this image I is stored in the memory (
(not shown).

In this way, only the image information of the first image @I is written into the memory in which the image information of FIG. 1 CB+ is stored,
As a result, the image information shown in FIG. 1 (Q) is stored in the memory.

In addition, a signal indicating that the first bit of the control information from the CPU is "10" is sent to the input terminal 18, and a l10WIL signal that the first bit of the control information from the CPU is "0" is sent to the input terminal 7.
T signal, I specifying 7 lip-flop 5 to input terminal 9
When the signal output from the output terminal Q of the flip-flop 5 is set to "0" by supplying 10 address signals from the CPU, the NAND circuit 10 always outputs "1", and the AND circuit 11 outputs "1" from the input terminal 6. The MWRT signal from the comparator circuit 4 is outputted as it is from the output terminal 12 regardless of (8), and all the image information input to the input terminals 1a to 1h is written to a memory (not shown).

In this way, as the image information is transmitted from the CPU to the memory, the hardware identifies for each pixel whether or not it is writable pixel information, so there is no need for extra time compared to software-based identification. Although the pixel information is 8 bits in the explanation, it may be other than 8 bits, and the pixel information may also be □, which does not include hue or saturation, and may also represent only brightness. Note that in the above embodiment, only one type of pixel information is identified so as not to be stored in the memory, but several sets of data registers, specific soft circuits, D-type flip-flops, NAND circuits,
An AND circuit may be provided with the same configuration as the circuit shown in FIG. 3, and the output of each set of AND circuits may be identified, and the present invention is not limited to the above embodiment.

As described above, the data identification write control device according to the present invention writes into the memory the second image information transmitted along with the control signal instructing the writing timing of each pixel to the memory storing the first image information. The same pixel information as unnecessary pixel information is stored in advance in a storage element different from the memory,
Each pixel of the second image information is compared with the pixel information of the storage element, and when they match, the control signal accompanying the pixel of the second image information is cut off and the pixel of the second image information is stored in the memory. This eliminates the time required for conventional software to identify whether or not the second image information can be written for each pixel, and has the advantage of shortening the time required for image composition processing. It is something that you have.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 to (g) are time charts of image information stored in the memory, respectively, and Fig. 3 is a block system diagram of one embodiment of the data identification writing control device according to the present invention. . la ~ lh, 6, 7, 9*・* input terminal, 2a ~ 2
h, 12/0 output terminal, 3rd/7th register,
4.0 comparison circuit, 5.. conflict frizz flop, l. ...Nand circuit, 1l-e-and circuit.

Claims (1)

[Claims] The same pixel information as the pixel information that does not need to be written into the memory in the second image quality information transmitted together with a control signal instructing the writing timing of each pixel to the memory storing the first image information. is stored in advance in another storage element,
Each pixel of the second image information is compared with the pixel information of the storage element, and when they match, the control signal associated with the pixel of the second image information is cut off and the second image is stored. A data identification write control device configured to prevent pixels of information from being written to the memory.