JPH06139136A - Display memory access system - Google Patents

Abstract

PURPOSE:To allow a host to access a bit map memory without being conscious of a boundary between upper and lower picture memories by preparing a register for setting up the center address of a display and an address conversion part. CONSTITUTION:At the time of receiving an access address from an address bus 6, the address conversion part 4 compares the received address with a center address value stored in the register 3, and when the access address is less than the center address value, generates a selection signal 9 for driving an upper side memory block 1 and supplies the inputted access address to a memory block 1 as it is to execute reading/writing access operation. When the access address is more than the center address value, the conversion part 4 outputs a selection signal 10 for driving a lower side memory block 2 and supplies a difference between the inputted access address and the center address value as the address of the memory block 2 to execute access operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display which is physically allocated to the upper and lower display areas of a display which is vertically divided.
The present invention relates to a display memory access method of a display control device having a display memory composed of a block bitmap memory.

Display devices are provided in various information processing devices (terminal devices, personal computers, word processors, workstations, etc.). Using an LCD (liquid crystal) as the display device of the display device,
Devices for reducing size and weight have come into wide use.
In the case of such an LCD, when a large screen having a large number of pixels for realizing a fine display is realized, there is a technical problem and a cost problem when it is configured with one display device, and therefore two display devices are required. A method is used in which the display screens are connected to each other by using the above to configure one display screen. In that case,
A display memory (frame memory) is composed of two bitmap memories for displaying on each display element, but it is necessary to be aware of two display areas when the display memory is accessed from the host side. .

[0003]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional example, and FIG. 5 is a diagram showing a relationship between an address viewed from a host on a display of the conventional example and an address area of a display memory.

In FIG. 4, 40 is a memory block for upper display, 41 is a memory block for lower display, 42 is a frame memory control circuit for accessing and reading and writing each memory block, 4
3 is a host, 44 is an address bus, 45 is a data bus, and 46 and 47 are block selection signals.

Memory blocks 40 and 41 are bit map memories for displaying an upper display and a lower display (not shown) which form a display screen.
A frame (display) memory is composed of one memory block. In this example, memory blocks 40 and 41 have 25
It is composed of a 6K-bit dual port memory (writing and reading can be performed in parallel).

For the frame memory composed of these two memory blocks 40 and 41, a. The address seen by the host on the display, b. Shows the area of the frame memory on the host.

FIG. 5 a. As shown in Fig. 7, the display is processed as having 640 pixels in the horizontal direction and 480 pixels in the vertical direction, but the address of each pixel in the 240 lines in the upper part of the display is 0000.
(H: hexadecimal) to 4 AFF (H), 240 on the lower side
The address of each pixel on the line is 8000 (H) to CAFF
Is.

In this case, the last upper address "4AF
The reason why "F" and the lower head address "8000" are discontinuous will be described. FIG. 5b. As shown in, the frame memory area is composed of the memory block 40 and the memory block 41. Since each memory block is a 256 Kbit dual port memory, the address next to the last address “4AFF” of the upper memory block 40 is This is because even if “4B00” is assigned as the start address of the lower memory block 41, the address “4B00” of the upper memory block 40 will be accessed.

That is, the address area of the upper memory block is b. Address "0000" as shown in
Indicates the top (upper left corner) pixel information on the display 8
Bits are stored, and 8 bits representing the next pixel information are stored in the address “0001”.
Up to "F", pixel information on the display is stored in order to form a display area. However, the addresses "4B00" to "7FFF" of the upper memory block 40 are
It is a non-display area where a memory area physically exists but pixel information is not stored.

In the lower memory block 41, the head is assigned the address "8000" by the host, and the addresses up to the address "CAFF" are designated as the display area. The addresses "CB00" to "F00" are used.
Up to "FFF" is a non-display area like the upper memory block.

As described above, the address viewed from the host on the display flies at the boundary between the upper display area and the lower display area. Therefore, when the host 43 accesses the memory block in FIG. When the control circuit 42 receives an address, it determines which memory block to access and generates a selection signal 46 or 47 for driving one of them.

[0012]

As described above, in the conventional configuration, since the frame memory area viewed from the host cannot be accessed as a continuous area, the host must access in consideration of the boundary between the upper and lower display areas. However, there is a problem that access control becomes complicated.

According to the present invention, in a display controller having two sets of bitmap memory blocks for display screens using upper and lower display devices, the host can access the bitmap memory without being aware of the boundaries of the upper and lower screen memories. It is an object of the present invention to provide a display memory access method capable of performing

[0014]

FIG. 1 is a basic configuration diagram of the present invention. In FIG. 1, 1 is a memory block for upper display, 2 is a memory block for lower display,
3 is a register (DCAR) in which a median value (display center address: DCA) on the display is set,
Reference numeral 4 is an address conversion unit, and 5 is a host. Reference numerals 6 and 8 are address buses, 7 is a data bus, and 9 and 10 are selection signals for the memory blocks 1 and 2, respectively.

According to the present invention, a register for setting a central address of the display (a boundary address between a memory block for the upper display and a memory block for the lower display) is provided, and an access address for continuing the upper and lower display areas is supplied from the host. Then, the access address and the central address of the display are calculated by the address conversion unit, and one of the memory blocks is selected and addressed by the output.

[0016]

Operation: First, the central address of the display screen is assigned to the register 3 (when the upper and lower screen addresses on the display are allocated, the top value of the lower memory map is set.

In the host, even if the display screen of the display is divided into upper and lower parts and the upper and lower screens are divided into the memory block 1 and the memory block 2 as the bit map memory,
The display areas of the two memory blocks are accessed assuming that consecutive addresses are assigned. When the address translation unit 4 receives the access address from the address bus 6, it compares it with the central address value of the register 3, and when the access address is less than the central address value, it generates a selection signal 9 for driving the upper memory block 1. Then, the input access address is directly supplied to the memory block 1 to perform read and write access operations. When the value is equal to or larger than the central address value of the register 3, the selection signal 10 for driving the lower memory block 2 is generated and the difference between the input access address and the central address value is supplied as the address of the memory block 2. Perform access operation.

[0018]

FIG. 2 is a block diagram of an embodiment, and FIG. 3 is a diagram showing a concrete example of addresses on a display and memory according to the present invention.

In FIG. 2, reference numerals 1, 2, 3, 5 and 6 are the same as those of the reference numerals in FIG. 1, 1 is an upper display memory block, 2 is a lower display memory block, and 3 is a display. A register (DCAR) for holding the median value (DCA) of the host, 5 is a host, and 6 is an address bus from the host.

In the internal configuration of the address conversion unit 4 in FIG. 2, 4a is a subtracter for subtracting (value of register 3)-(access address from host), and 400 is a difference (positive) , Both negative), 401 is a borrow signal that is output when the difference is 0 or negative, 4b is a selector (SEL), and 4c is an inverter that performs a negative logic operation.

The subtractor 4a is the median value set in the register 3 (it is the address of the leading pixel of the lower display).
Subtract the access address from the host from
When the value of (register 3)-(access address from host) ≤0, the borrow signal is logical "1", and in other cases, the borrow signal is logical "0".

In FIG. 3, a is an address seen from the host on the display, b is a frame (display) memory area on the host, and c is an address area of each memory block.

The operation of the embodiment of FIG. 2 will be described with reference to the concrete example of FIG. When an upper address on the display among the addresses shown in FIG. 3A, for example, "004F" is generated as an access address from the host, the address of the top pixel of the lower display as the median value in the register 3, "4B00" in this example. Is set and the subtractor 4a executes the subtraction of "value of register 3-access address". Therefore, in this example, the value of register 3 (= 4B
00) is larger than the access address (= 004F), the output of the borrow signal 401 is "0".

On the other hand, the borrow signal 401 is directly supplied to the upper memory block 1 as the selection signal 9, and the signal inverted by the inverter 4c is supplied as the selection signal 10 to the lower memory block 2 to select in any case. When the signal is logic "0", the memory block is driven.

Therefore, when the borrow signal 401 is "0", the selector 4b selects the access address directly input from the host 5 and supplies it to the upper memory block 1 selected by the selection signal 9. That is, as for the pixel address of the upper screen as viewed from the host, the address value is directly supplied to the upper memory block 1 to perform the access operation.

The host 5 accesses as a continuous area as shown in FIG. 3a regardless of the boundary addresses of the upper and lower memory blocks. For example, the host 5 accesses the lower screen pixel address "4B01" on the display of FIG. 3a. If "" is selected, subtraction is performed in the subtractor 4a, (4B00)-
In the case of (4B01), since the result is "-1", the value of the differential signal 400 is "1" and the borrow signal 401 is a logical "1". Therefore, since the control signal is "1", the selector 4b of FIG. 2 selects the difference signal of the access address of the host and the difference signal 400. On the other hand, "1" of the borrow signal 401 is inverted to "0" by the inverter 4c to drive the lower memory block 2 as the selection signal 10. In this case, the lower memory block is assumed to access the address 8001 of the lower memory block shown in FIG. 3C when the difference value “1” is input as an address. Other addresses are accessed in the same manner.

[0027]

According to the present invention, in a display control device using two sets of upper and lower display devices and using two sets of memory blocks corresponding to respective displays, the host sets boundaries between upper and lower screen memories. The display (frame) memory can be accessed without being aware of it, and access control is simplified.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a diagram showing a specific example of an address on a display and an address on a memory according to the present invention.

FIG. 4 is a configuration diagram of a conventional example.

FIG. 5 is a diagram showing a relationship between an address viewed from a host on a display and an address area of a display memory in a conventional example.

[Explanation of symbols]

 1 Memory block for upper display 2 Memory block for lower display 3 Register (DCAR) in which median value is set 4 Address converter 5 Host 6, 8 Address bus 7 Data bus 9 Selection signal of memory block 1 10 Memory block 2 Selection signal

Claims (2)

[Claims] 1. A display control device having a display memory consisting of two blocks of bitmap memory physically allocated to the upper and lower display areas of a vertically controlled display, and a register for setting a top pixel address of a lower screen. And an address conversion unit that compares the access address input from the host to the bit map memory with the address set in the register to generate the address of the display memory, and outputs the bits of the two blocks by the output of the address conversion unit. A display memory access method characterized in that one of the map memories is selected, an address corresponding to each block is generated, and the host is accessed without being aware of the address boundary of the two blocks of the bitmap memory. 2. The address conversion unit according to claim 1, when the display memory is accessed from the host, subtracts an access address value from the host from a set value of the register to generate a difference between two values and a borrow signal. A subtracter is provided, and the borrow signal from the subtractor is supplied as a selection signal of the bit map memory of the above two blocks. When the borrow signal is not generated, the access address from the host is used as it is, and the borrow signal is generated. A display memory access method, wherein the difference of the subtractor is used as an access address.